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1 From d9b391e7b695b7de04c4363b5ec9ffaaed387353 Mon Sep 17 00:00:00 2001
2 From: Luo Jie <quic_luoj@quicinc.com>
3 Date: Wed, 8 Nov 2023 18:01:14 +0800
4 Subject: [PATCH 04/50] net: phy: qca808x: Add link_change_notify function for
5 QCA8084
6
7 When the link is changed, QCA8084 needs to do the fifo reset and
8 adjust the IPG level for the 10G-QXGMII link on the speed 1000M.
9
10 Change-Id: I21de802c78496fb95f1c5119fe3894c9fdebbd65
11 Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
12 ---
13 drivers/net/phy/qcom/qca808x.c | 52 ++++++++++++++++++++++++++++++++++
14 1 file changed, 52 insertions(+)
15
16 --- a/drivers/net/phy/qcom/qca808x.c
17 +++ b/drivers/net/phy/qcom/qca808x.c
18 @@ -103,6 +103,14 @@
19 #define QCA8084_MSE_THRESHOLD 0x800a
20 #define QCA8084_MSE_THRESHOLD_2P5G_VAL 0x51c6
21
22 +/* QCA8084 FIFO reset control */
23 +#define QCA8084_FIFO_CONTROL 0x19
24 +#define QCA8084_FIFO_MAC_2_PHY BIT(1)
25 +#define QCA8084_FIFO_PHY_2_MAC BIT(0)
26 +
27 +#define QCA8084_MMD7_IPG_OP 0x901d
28 +#define QCA8084_IPG_10_TO_11_EN BIT(0)
29 +
30 MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
31 MODULE_AUTHOR("Matus Ujhelyi, Luo Jie");
32 MODULE_LICENSE("GPL");
33 @@ -697,6 +705,49 @@ static int qca8084_config_init(struct ph
34 QCA8084_MSE_THRESHOLD_2P5G_VAL);
35 }
36
37 +static void qca8084_link_change_notify(struct phy_device *phydev)
38 +{
39 + int ret;
40 +
41 + /* Assert the FIFO between PHY and MAC. */
42 + ret = phy_modify(phydev, QCA8084_FIFO_CONTROL,
43 + QCA8084_FIFO_MAC_2_PHY | QCA8084_FIFO_PHY_2_MAC,
44 + 0);
45 + if (ret) {
46 + phydev_err(phydev, "Asserting PHY FIFO failed\n");
47 + return;
48 + }
49 +
50 + /* If the PHY is in 10G_QXGMII mode, the FIFO needs to be kept in
51 + * reset state when link is down, otherwise the FIFO needs to be
52 + * de-asserted after waiting 50 ms to make the assert completed.
53 + */
54 + if (phydev->interface != PHY_INTERFACE_MODE_10G_QXGMII ||
55 + phydev->link) {
56 + msleep(50);
57 +
58 + /* Deassert the FIFO between PHY and MAC. */
59 + ret = phy_modify(phydev, QCA8084_FIFO_CONTROL,
60 + QCA8084_FIFO_MAC_2_PHY |
61 + QCA8084_FIFO_PHY_2_MAC,
62 + QCA8084_FIFO_MAC_2_PHY |
63 + QCA8084_FIFO_PHY_2_MAC);
64 + if (ret) {
65 + phydev_err(phydev, "De-asserting PHY FIFO failed\n");
66 + return;
67 + }
68 + }
69 +
70 + /* Enable IPG level 10 to 11 tuning for link speed 1000M in the
71 + * 10G_QXGMII mode.
72 + */
73 + if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII)
74 + phy_modify_mmd(phydev, MDIO_MMD_AN, QCA8084_MMD7_IPG_OP,
75 + QCA8084_IPG_10_TO_11_EN,
76 + phydev->speed == SPEED_1000 ?
77 + QCA8084_IPG_10_TO_11_EN : 0);
78 +}
79 +
80 static struct phy_driver qca808x_driver[] = {
81 {
82 /* Qualcomm QCA8081 */
83 @@ -746,6 +797,7 @@ static struct phy_driver qca808x_driver[
84 .cable_test_start = qca808x_cable_test_start,
85 .cable_test_get_status = qca808x_cable_test_get_status,
86 .config_init = qca8084_config_init,
87 + .link_change_notify = qca8084_link_change_notify,
88 }, };
89
90 module_phy_driver(qca808x_driver);