git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From b033dfb21df8ae876ec69d84bc8c5fafd7aa8ced Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Fri, 17 Jan 2025 17:16:38 +0800
   4 Subject: [PATCH 02/15] clk: mediatek: fix uninitialized fields issue in
   5  INFRA_MUX struct
   6
   7 This patch adds missing initialization of fields in INFRA_MUX struct
   8 which caused uart broken after any other infra mux being enabled by
   9 'clk_prepare_enable'
  10
  11 Signed-off-by: Sam Shih <sam.shih@mediatek.com>
  12 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  13 ---
  14  drivers/clk/mediatek/clk-mt7981.c | 1 +
  15  drivers/clk/mediatek/clk-mt7986.c | 1 +
  16  drivers/clk/mediatek/clk-mt7988.c | 1 +
  17  3 files changed, 3 insertions(+)
  18
  19 --- a/drivers/clk/mediatek/clk-mt7981.c
  20 +++ b/drivers/clk/mediatek/clk-mt7981.c
  21 @@ -359,6 +359,7 @@ static const struct mtk_parent infra_pci
  22                 .id = _id, .mux_reg = (_reg) + 0x8,                            \
  23                 .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4,      \
  24                 .mux_shift = _shift, .mux_mask = BIT(_width) - 1,              \
  25 +               .gate_shift = -1, .upd_shift = -1,                             \
  26                 .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
  27                 .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED,                \
  28         }
  29 --- a/drivers/clk/mediatek/clk-mt7986.c
  30 +++ b/drivers/clk/mediatek/clk-mt7986.c
  31 @@ -366,6 +366,7 @@ static const struct mtk_parent infra_pci
  32                 .id = _id, .mux_reg = (_reg) + 0x8,                            \
  33                 .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4,      \
  34                 .mux_shift = _shift, .mux_mask = BIT(_width) - 1,              \
  35 +               .gate_shift = -1, .upd_shift = -1,                             \
  36                 .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
  37                 .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED,                \
  38         }
  39 --- a/drivers/clk/mediatek/clk-mt7988.c
  40 +++ b/drivers/clk/mediatek/clk-mt7988.c
  41 @@ -485,6 +485,7 @@ static const int infra_pcie_gfmux_tl_ck_
  42                 .id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0,   \
  43                 .mux_clr_reg = _reg + 0x4, .mux_shift = _shift,                \
  44                 .mux_mask = BIT(_width) - 1, .parent = _parents,               \
  45 +               .gate_shift = -1, .upd_shift = -1,                             \
  46                 .num_parents = ARRAY_SIZE(_parents),                           \
  47                 .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN,             \
  48         }