git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From c0f1cbf795095c21b92a46fa1dc47a7b787ce538 Mon Sep 17 00:00:00 2001
   2 From: Luo Jie <quic_luoj@quicinc.com>
   3 Date: Fri, 3 Jan 2025 15:31:34 +0800
   4 Subject: [PATCH 1/3] dt-bindings: clock: qcom: Add CMN PLL clock controller
   5  for IPQ SoC
   6
   7 The CMN PLL controller provides clocks to networking hardware blocks
   8 and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the
   9 on-chip Wi-Fi, and produces output clocks at fixed rates. These output
  10 rates are predetermined, and are unrelated to the input clock rate.
  11 The primary purpose of CMN PLL is to supply clocks to the networking
  12 hardware such as PPE (packet process engine), PCS and the externally
  13 connected switch or PHY device. The CMN PLL block also outputs fixed
  14 rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep
  15 clock supplied to GCC.
  16
  17 Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
  18 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  19 Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com
  20 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  21 ---
  22  .../bindings/clock/qcom,ipq9574-cmn-pll.yaml  | 77 +++++++++++++++++++
  23  include/dt-bindings/clock/qcom,ipq-cmn-pll.h  | 22 ++++++
  24  2 files changed, 99 insertions(+)
  25  create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
  26  create mode 100644 include/dt-bindings/clock/qcom,ipq-cmn-pll.h
  27
  28 --- /dev/null
  29 +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
  30 @@ -0,0 +1,77 @@
  31 +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  32 +%YAML 1.2
  33 +---
  34 +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
  35 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  36 +
  37 +title: Qualcomm CMN PLL Clock Controller on IPQ SoC
  38 +
  39 +maintainers:
  40 +  - Bjorn Andersson <andersson@kernel.org>
  41 +  - Luo Jie <quic_luoj@quicinc.com>
  42 +
  43 +description:
  44 +  The CMN (or common) PLL clock controller expects a reference
  45 +  input clock. This reference clock is from the on-board Wi-Fi.
  46 +  The CMN PLL supplies a number of fixed rate output clocks to
  47 +  the devices providing networking functions and to GCC. These
  48 +  networking hardware include PPE (packet process engine), PCS
  49 +  and the externally connected switch or PHY devices. The CMN
  50 +  PLL block also outputs fixed rate clocks to GCC. The PLL's
  51 +  primary function is to enable fixed rate output clocks for
  52 +  networking hardware functions used with the IPQ SoC.
  53 +
  54 +properties:
  55 +  compatible:
  56 +    enum:
  57 +      - qcom,ipq9574-cmn-pll
  58 +
  59 +  reg:
  60 +    maxItems: 1
  61 +
  62 +  clocks:
  63 +    items:
  64 +      - description: The reference clock. The supported clock rates include
  65 +          25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.
  66 +      - description: The AHB clock
  67 +      - description: The SYS clock
  68 +    description:
  69 +      The reference clock is the source clock of CMN PLL, which is from the
  70 +      Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
  71 +      clock registers.
  72 +
  73 +  clock-names:
  74 +    items:
  75 +      - const: ref
  76 +      - const: ahb
  77 +      - const: sys
  78 +
  79 +  "#clock-cells":
  80 +    const: 1
  81 +
  82 +required:
  83 +  - compatible
  84 +  - reg
  85 +  - clocks
  86 +  - clock-names
  87 +  - "#clock-cells"
  88 +
  89 +additionalProperties: false
  90 +
  91 +examples:
  92 +  - |
  93 +    #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
  94 +    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
  95 +
  96 +    cmn_pll: clock-controller@9b000 {
  97 +        compatible = "qcom,ipq9574-cmn-pll";
  98 +        reg = <0x0009b000 0x800>;
  99 +        clocks = <&cmn_pll_ref_clk>,
 100 +                 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
 101 +                 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
 102 +        clock-names = "ref", "ahb", "sys";
 103 +        #clock-cells = <1>;
 104 +        assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
 105 +        assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
 106 +    };
 107 +...
 108 --- /dev/null
 109 +++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
 110 @@ -0,0 +1,22 @@
 111 +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
 112 +/*
 113 + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 114 + */
 115 +
 116 +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
 117 +#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
 118 +
 119 +/* CMN PLL core clock. */
 120 +#define CMN_PLL_CLK                    0
 121 +
 122 +/* The output clocks from CMN PLL of IPQ9574. */
 123 +#define XO_24MHZ_CLK                   1
 124 +#define SLEEP_32KHZ_CLK                        2
 125 +#define PCS_31P25MHZ_CLK               3
 126 +#define NSS_1200MHZ_CLK                        4
 127 +#define PPE_353MHZ_CLK                 5
 128 +#define ETH0_50MHZ_CLK                 6
 129 +#define ETH1_50MHZ_CLK                 7
 130 +#define ETH2_50MHZ_CLK                 8
 131 +#define ETH_25MHZ_CLK                  9
 132 +#endif