git.ipfire.org Git - thirdparty/kernel/linux.git/blob

   1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings
   8
   9 maintainers:
  10   - Helen Koike <helen.koike@collabora.com>
  11   - Ezequiel Garcia <ezequiel@collabora.com>
  12
  13 description: |
  14   The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
  15   the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
  16
  17 properties:
  18   compatible:
  19     const: rockchip,rk3399-mipi-dphy-rx0
  20
  21   reg:
  22     maxItems: 1
  23
  24   clocks:
  25     items:
  26       - description: MIPI D-PHY ref clock
  27       - description: MIPI D-PHY RX0 cfg clock
  28       - description: Video in/out general register file clock
  29
  30   clock-names:
  31     items:
  32       - const: dphy-ref
  33       - const: dphy-cfg
  34       - const: grf
  35
  36   '#phy-cells':
  37     const: 0
  38
  39   power-domains:
  40     description: Video in/out power domain.
  41     maxItems: 1
  42
  43 required:
  44   - compatible
  45   - clocks
  46   - clock-names
  47   - '#phy-cells'
  48   - power-domains
  49
  50 additionalProperties: false
  51
  52 examples:
  53   - |
  54
  55     /*
  56      * MIPI D-PHY RX0 use registers in "general register files", it
  57      * should be a child of the GRF.
  58      *
  59      * grf: syscon@ff770000 {
  60      *  compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
  61      *  ...
  62      * };
  63      */
  64
  65     #include <dt-bindings/clock/rk3399-cru.h>
  66     #include <dt-bindings/power/rk3399-power.h>
  67
  68     mipi_dphy_rx0: mipi-dphy-rx0 {
  69         compatible = "rockchip,rk3399-mipi-dphy-rx0";
  70         clocks = <&cru SCLK_MIPIDPHY_REF>,
  71                  <&cru SCLK_DPHY_RX0_CFG>,
  72                  <&cru PCLK_VIO_GRF>;
  73         clock-names = "dphy-ref", "dphy-cfg", "grf";
  74         power-domains = <&power RK3399_PD_VIO>;
  75         #phy-cells = <0>;
  76     };