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1 From ca024bc7267a8c0439325d352f9b8818ba0f2cf0 Mon Sep 17 00:00:00 2001
2 From: "SkyLake.Huang" <skylake.huang@mediatek.com>
3 Date: Fri, 4 Oct 2024 18:24:13 +0800
4 Subject: [PATCH 9/9] net: phy: mediatek: Add token ring access helper
5 functions in mtk-phy-lib
6
7 This patch adds TR(token ring) manipulations and adds correct
8 macro names for those magic numbers. TR is a way to access
9 proprietary registers on page 52b5. Use these helper functions
10 so we can see which fields we're going to modify/set/clear.
11
12 This patch doesn't really change registers' settings but just
13 enhances readability and maintainability.
14
15 Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
16 ---
17 drivers/net/phy/mediatek/mtk-ge-soc.c | 297 ++++++++++++++++---------
18 drivers/net/phy/mediatek/mtk-ge.c | 82 +++++--
19 drivers/net/phy/mediatek/mtk-phy-lib.c | 91 ++++++++
20 drivers/net/phy/mediatek/mtk.h | 13 ++
21 4 files changed, 358 insertions(+), 125 deletions(-)
22
23 --- a/drivers/net/phy/mediatek/mtk-ge-soc.c
24 +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
25 @@ -24,7 +24,108 @@
26 #define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
27
28 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
29 -#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
30 +
31 +/* Registers on Token Ring debug nodes */
32 +/* ch_addr = 0x0, node_addr = 0x7, data_addr = 0x15 */
33 +/* NormMseLoThresh */
34 +#define NORMAL_MSE_LO_THRESH_MASK GENMASK(15, 8)
35 +
36 +/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
37 +/* RemAckCntLimitCtrl */
38 +#define REMOTE_ACK_COUNT_LIMIT_CTRL_MASK GENMASK(2, 1)
39 +
40 +/* ch_addr = 0x1, node_addr = 0xd, data_addr = 0x20 */
41 +/* VcoSlicerThreshBitsHigh */
42 +#define VCO_SLICER_THRESH_HIGH_MASK GENMASK(23, 0)
43 +
44 +/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x0 */
45 +/* DfeTailEnableVgaThresh1000 */
46 +#define DFE_TAIL_EANBLE_VGA_TRHESH_1000 GENMASK(5, 1)
47 +
48 +/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x1 */
49 +/* MrvlTrFix100Kp */
50 +#define MRVL_TR_FIX_100KP_MASK GENMASK(22, 20)
51 +/* MrvlTrFix100Kf */
52 +#define MRVL_TR_FIX_100KF_MASK GENMASK(19, 17)
53 +/* MrvlTrFix1000Kp */
54 +#define MRVL_TR_FIX_1000KP_MASK GENMASK(16, 14)
55 +/* MrvlTrFix1000Kf */
56 +#define MRVL_TR_FIX_1000KF_MASK GENMASK(13, 11)
57 +
58 +/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x12 */
59 +/* VgaDecRate */
60 +#define VGA_DECIMATION_RATE_MASK GENMASK(8, 5)
61 +
62 +/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
63 +/* SlvDSPreadyTime */
64 +#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)
65 +/* MasDSPreadyTime */
66 +#define MASTER_DSP_READY_TIME_MASK GENMASK(14, 7)
67 +
68 +/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x18 */
69 +/* EnabRandUpdTrig */
70 +#define ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER BIT(8)
71 +
72 +/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */
73 +/* ResetSyncOffset */
74 +#define RESET_SYNC_OFFSET_MASK GENMASK(11, 8)
75 +
76 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x0 */
77 +/* FfeUpdGainForceVal */
78 +#define FFE_UPDATE_GAIN_FORCE_VAL_MASK GENMASK(9, 7)
79 +/* FfeUpdGainForce */
80 +#define FFE_UPDATE_GAIN_FORCE BIT(6)
81 +
82 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x3 */
83 +/* TrFreeze */
84 +#define TR_FREEZE_MASK GENMASK(11, 0)
85 +
86 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */
87 +/* SS: Steady-state, KP: Proportional Gain */
88 +/* SSTrKp100 */
89 +#define SS_TR_KP100_MASK GENMASK(21, 19)
90 +/* SSTrKf100 */
91 +#define SS_TR_KF100_MASK GENMASK(18, 16)
92 +/* SSTrKp1000Mas */
93 +#define SS_TR_KP1000_MASTER_MASK GENMASK(15, 13)
94 +/* SSTrKf1000Mas */
95 +#define SS_TR_KF1000_MASTER_MASK GENMASK(12, 10)
96 +/* SSTrKp1000Slv */
97 +#define SS_TR_KP1000_SLAVE_MASK GENMASK(9, 7)
98 +/* SSTrKf1000Slv */
99 +#define SS_TR_KF1000_SLAVE_MASK GENMASK(6, 4)
100 +
101 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x8 */
102 +/* clear this bit if wanna select from AFE */
103 +/* Regsigdet_sel_1000 */
104 +#define EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE BIT(4)
105 +
106 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */
107 +/* RegEEE_st2TrKf1000 */
108 +#define EEE1000_STAGE2_TR_KF_MASK GENMASK(13, 11)
109 +
110 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xf */
111 +/* RegEEE_slv_waketr_timer_tar */
112 +#define SLAVE_WAKETR_TIMER_MASK GENMASK(20, 11)
113 +/* RegEEE_slv_remtx_timer_tar */
114 +#define SLAVE_REMTX_TIMER_MASK GENMASK(10, 1)
115 +
116 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x10 */
117 +/* RegEEE_slv_wake_int_timer_tar */
118 +#define SLAVE_WAKEINT_TIMER_MASK GENMASK(10, 1)
119 +
120 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x14 */
121 +/* RegEEE_trfreeze_timer2 */
122 +#define TR_FREEZE_TIMER2_MASK GENMASK(9, 0)
123 +
124 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x1c */
125 +/* RegEEE100Stg1_tar */
126 +#define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK GENMASK(8, 0)
127 +
128 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x25 */
129 +/* REGEEE_wake_slv_tr_wait_dfesigdet_en */
130 +#define WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN BIT(11)
131 +
132
133 #define ANALOG_INTERNAL_OPERATION_MAX_US 20
134 #define TXRESERVE_MIN 0
135 @@ -679,40 +780,36 @@ restore:
136 static void mt798x_phy_common_finetune(struct phy_device *phydev)
137 {
138 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
139 - /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
140 - __phy_write(phydev, 0x11, 0xc71);
141 - __phy_write(phydev, 0x12, 0xc);
142 - __phy_write(phydev, 0x10, 0x8fae);
143 -
144 - /* EnabRandUpdTrig = 1 */
145 - __phy_write(phydev, 0x11, 0x2f00);
146 - __phy_write(phydev, 0x12, 0xe);
147 - __phy_write(phydev, 0x10, 0x8fb0);
148 -
149 - /* NormMseLoThresh = 85 */
150 - __phy_write(phydev, 0x11, 0x55a0);
151 - __phy_write(phydev, 0x12, 0x0);
152 - __phy_write(phydev, 0x10, 0x83aa);
153 -
154 - /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
155 - __phy_write(phydev, 0x11, 0x240);
156 - __phy_write(phydev, 0x12, 0x0);
157 - __phy_write(phydev, 0x10, 0x9680);
158 -
159 - /* TrFreeze = 0 (mt7988 default) */
160 - __phy_write(phydev, 0x11, 0x0);
161 - __phy_write(phydev, 0x12, 0x0);
162 - __phy_write(phydev, 0x10, 0x9686);
163 -
164 - /* SSTrKp100 = 5 */
165 - /* SSTrKf100 = 6 */
166 - /* SSTrKp1000Mas = 5 */
167 - /* SSTrKf1000Mas = 6 */
168 - /* SSTrKp1000Slv = 5 */
169 - /* SSTrKf1000Slv = 6 */
170 - __phy_write(phydev, 0x11, 0xbaef);
171 - __phy_write(phydev, 0x12, 0x2e);
172 - __phy_write(phydev, 0x10, 0x968c);
173 + __mtk_tr_modify(phydev, 0x1, 0xf, 0x17,
174 + SLAVE_DSP_READY_TIME_MASK | MASTER_DSP_READY_TIME_MASK,
175 + FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x18) |
176 + FIELD_PREP(MASTER_DSP_READY_TIME_MASK, 0x18));
177 +
178 + __mtk_tr_set_bits(phydev, 0x1, 0xf, 0x18,
179 + ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER);
180 +
181 + __mtk_tr_modify(phydev, 0x0, 0x7, 0x15,
182 + NORMAL_MSE_LO_THRESH_MASK,
183 + FIELD_PREP(NORMAL_MSE_LO_THRESH_MASK, 0x55));
184 +
185 + __mtk_tr_modify(phydev, 0x2, 0xd, 0x0,
186 + FFE_UPDATE_GAIN_FORCE_VAL_MASK,
187 + FIELD_PREP(FFE_UPDATE_GAIN_FORCE_VAL_MASK, 0x4) |
188 + FFE_UPDATE_GAIN_FORCE);
189 +
190 + __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x3, TR_FREEZE_MASK);
191 +
192 + __mtk_tr_modify(phydev, 0x2, 0xd, 0x6,
193 + SS_TR_KP100_MASK | SS_TR_KF100_MASK |
194 + SS_TR_KP1000_MASTER_MASK | SS_TR_KF1000_MASTER_MASK |
195 + SS_TR_KP1000_SLAVE_MASK | SS_TR_KF1000_SLAVE_MASK,
196 + FIELD_PREP(SS_TR_KP100_MASK, 0x5) |
197 + FIELD_PREP(SS_TR_KF100_MASK, 0x6) |
198 + FIELD_PREP(SS_TR_KP1000_MASTER_MASK, 0x5) |
199 + FIELD_PREP(SS_TR_KF1000_MASTER_MASK, 0x6) |
200 + FIELD_PREP(SS_TR_KP1000_SLAVE_MASK, 0x5) |
201 + FIELD_PREP(SS_TR_KF1000_SLAVE_MASK, 0x6));
202 +
203 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
204 }
205
206 @@ -735,27 +832,29 @@ static void mt7981_phy_finetune(struct p
207 }
208
209 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
210 - /* ResetSyncOffset = 6 */
211 - __phy_write(phydev, 0x11, 0x600);
212 - __phy_write(phydev, 0x12, 0x0);
213 - __phy_write(phydev, 0x10, 0x8fc0);
214 -
215 - /* VgaDecRate = 1 */
216 - __phy_write(phydev, 0x11, 0x4c2a);
217 - __phy_write(phydev, 0x12, 0x3e);
218 - __phy_write(phydev, 0x10, 0x8fa4);
219 + __mtk_tr_modify(phydev, 0x1, 0xf, 0x20,
220 + RESET_SYNC_OFFSET_MASK,
221 + FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x6));
222 +
223 + __mtk_tr_modify(phydev, 0x1, 0xf, 0x12,
224 + VGA_DECIMATION_RATE_MASK,
225 + FIELD_PREP(VGA_DECIMATION_RATE_MASK, 0x1));
226
227 /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
228 * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
229 */
230 - __phy_write(phydev, 0x11, 0xd10a);
231 - __phy_write(phydev, 0x12, 0x34);
232 - __phy_write(phydev, 0x10, 0x8f82);
233 + __mtk_tr_modify(phydev, 0x1, 0xf, 0x1,
234 + MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK |
235 + MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK,
236 + FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x3) |
237 + FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x2) |
238 + FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x3) |
239 + FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x2));
240
241 /* VcoSlicerThreshBitsHigh */
242 - __phy_write(phydev, 0x11, 0x5555);
243 - __phy_write(phydev, 0x12, 0x55);
244 - __phy_write(phydev, 0x10, 0x8ec0);
245 + __mtk_tr_modify(phydev, 0x1, 0xd, 0x20,
246 + VCO_SLICER_THRESH_HIGH_MASK,
247 + FIELD_PREP(VCO_SLICER_THRESH_HIGH_MASK, 0x555555));
248 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
249
250 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
251 @@ -807,25 +906,23 @@ static void mt7988_phy_finetune(struct p
252 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
253
254 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
255 - /* ResetSyncOffset = 5 */
256 - __phy_write(phydev, 0x11, 0x500);
257 - __phy_write(phydev, 0x12, 0x0);
258 - __phy_write(phydev, 0x10, 0x8fc0);
259 + __mtk_tr_modify(phydev, 0x1, 0xf, 0x20,
260 + RESET_SYNC_OFFSET_MASK,
261 + FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x5));
262
263 /* VgaDecRate is 1 at default on mt7988 */
264
265 - /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
266 - * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
267 - */
268 - __phy_write(phydev, 0x11, 0xb90a);
269 - __phy_write(phydev, 0x12, 0x6f);
270 - __phy_write(phydev, 0x10, 0x8f82);
271 -
272 - /* RemAckCntLimitCtrl = 1 */
273 - __phy_write(phydev, 0x11, 0xfbba);
274 - __phy_write(phydev, 0x12, 0xc3);
275 - __phy_write(phydev, 0x10, 0x87f8);
276 -
277 + __mtk_tr_modify(phydev, 0x1, 0xf, 0x1,
278 + MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK |
279 + MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK,
280 + FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x6) |
281 + FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x7) |
282 + FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x6) |
283 + FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x7));
284 +
285 + __mtk_tr_modify(phydev, 0x0, 0xf, 0x3c,
286 + REMOTE_ACK_COUNT_LIMIT_CTRL_MASK,
287 + FIELD_PREP(REMOTE_ACK_COUNT_LIMIT_CTRL_MASK, 0x1));
288 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
289
290 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
291 @@ -901,45 +998,37 @@ static void mt798x_phy_eee(struct phy_de
292 MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
293
294 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
295 - /* Regsigdet_sel_1000 = 0 */
296 - __phy_write(phydev, 0x11, 0xb);
297 - __phy_write(phydev, 0x12, 0x0);
298 - __phy_write(phydev, 0x10, 0x9690);
299 -
300 - /* REG_EEE_st2TrKf1000 = 2 */
301 - __phy_write(phydev, 0x11, 0x114f);
302 - __phy_write(phydev, 0x12, 0x2);
303 - __phy_write(phydev, 0x10, 0x969a);
304 -
305 - /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
306 - __phy_write(phydev, 0x11, 0x3028);
307 - __phy_write(phydev, 0x12, 0x0);
308 - __phy_write(phydev, 0x10, 0x969e);
309 -
310 - /* RegEEE_slv_wake_int_timer_tar = 8 */
311 - __phy_write(phydev, 0x11, 0x5010);
312 - __phy_write(phydev, 0x12, 0x0);
313 - __phy_write(phydev, 0x10, 0x96a0);
314 -
315 - /* RegEEE_trfreeze_timer2 = 586 */
316 - __phy_write(phydev, 0x11, 0x24a);
317 - __phy_write(phydev, 0x12, 0x0);
318 - __phy_write(phydev, 0x10, 0x96a8);
319 -
320 - /* RegEEE100Stg1_tar = 16 */
321 - __phy_write(phydev, 0x11, 0x3210);
322 - __phy_write(phydev, 0x12, 0x0);
323 - __phy_write(phydev, 0x10, 0x96b8);
324 -
325 - /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
326 - __phy_write(phydev, 0x11, 0x1463);
327 - __phy_write(phydev, 0x12, 0x0);
328 - __phy_write(phydev, 0x10, 0x96ca);
329 -
330 - /* DfeTailEnableVgaThresh1000 = 27 */
331 - __phy_write(phydev, 0x11, 0x36);
332 - __phy_write(phydev, 0x12, 0x0);
333 - __phy_write(phydev, 0x10, 0x8f80);
334 + __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x8,
335 + EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE);
336 +
337 + __mtk_tr_modify(phydev, 0x2, 0xd, 0xd,
338 + EEE1000_STAGE2_TR_KF_MASK,
339 + FIELD_PREP(EEE1000_STAGE2_TR_KF_MASK, 0x2));
340 +
341 + __mtk_tr_modify(phydev, 0x2, 0xd, 0xf,
342 + SLAVE_WAKETR_TIMER_MASK | SLAVE_REMTX_TIMER_MASK,
343 + FIELD_PREP(SLAVE_WAKETR_TIMER_MASK, 0x6) |
344 + FIELD_PREP(SLAVE_REMTX_TIMER_MASK, 0x14));
345 +
346 + __mtk_tr_modify(phydev, 0x2, 0xd, 0x10,
347 + SLAVE_WAKEINT_TIMER_MASK,
348 + FIELD_PREP(SLAVE_WAKEINT_TIMER_MASK, 0x8));
349 +
350 + __mtk_tr_modify(phydev, 0x2, 0xd, 0x14,
351 + TR_FREEZE_TIMER2_MASK,
352 + FIELD_PREP(TR_FREEZE_TIMER2_MASK, 0x24a));
353 +
354 + __mtk_tr_modify(phydev, 0x2, 0xd, 0x1c,
355 + EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
356 + FIELD_PREP(EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
357 + 0x10));
358 +
359 + __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x25,
360 + WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN);
361 +
362 + __mtk_tr_modify(phydev, 0x1, 0xf, 0x0,
363 + DFE_TAIL_EANBLE_VGA_TRHESH_1000,
364 + FIELD_PREP(DFE_TAIL_EANBLE_VGA_TRHESH_1000, 0x1b));
365 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
366
367 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
368 --- a/drivers/net/phy/mediatek/mtk-ge.c
369 +++ b/drivers/net/phy/mediatek/mtk-ge.c
370 @@ -9,13 +9,35 @@
371 #define MTK_GPHY_ID_MT7530 0x03a29412
372 #define MTK_GPHY_ID_MT7531 0x03a29441
373
374 -#define MTK_EXT_PAGE_ACCESS 0x1f
375 -#define MTK_PHY_PAGE_STANDARD 0x0000
376 -#define MTK_PHY_PAGE_EXTENDED 0x0001
377 -#define MTK_PHY_PAGE_EXTENDED_2 0x0002
378 -#define MTK_PHY_PAGE_EXTENDED_3 0x0003
379 -#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
380 -#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
381 +#define MTK_PHY_PAGE_EXTENDED_1 0x0001
382 +#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14
383 +#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4)
384 +
385 +#define MTK_PHY_PAGE_EXTENDED_2 0x0002
386 +#define MTK_PHY_PAGE_EXTENDED_3 0x0003
387 +#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11 0x11
388 +
389 +#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
390 +
391 +/* Registers on Token Ring debug nodes */
392 +/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
393 +#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)
394 +
395 +/* Registers on MDIO_MMD_VEND1 */
396 +#define MTK_PHY_GBE_MODE_TX_DELAY_SEL 0x13
397 +#define MTK_PHY_TEST_MODE_TX_DELAY_SEL 0x14
398 +#define MTK_TX_DELAY_PAIR_B_MASK GENMASK(10, 8)
399 +#define MTK_TX_DELAY_PAIR_D_MASK GENMASK(2, 0)
400 +
401 +#define MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL 0xa6
402 +#define MTK_MCC_NEARECHO_OFFSET_MASK GENMASK(15, 8)
403 +
404 +#define MTK_PHY_RXADC_CTRL_RG7 0xc6
405 +#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
406 +
407 +#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123 0x123
408 +#define MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK GENMASK(15, 8)
409 +#define MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK GENMASK(7, 0)
410
411 struct mtk_gephy_priv {
412 unsigned long led_state;
413 @@ -27,20 +49,29 @@ static void mtk_gephy_config_init(struct
414 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
415
416 /* Enable HW auto downshift */
417 - phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
418 + phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1,
419 + MTK_PHY_AUX_CTRL_AND_STATUS,
420 + 0, MTK_PHY_ENABLE_DOWNSHIFT);
421
422 /* Increase SlvDPSready time */
423 - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
424 - __phy_write(phydev, 0x10, 0xafae);
425 - __phy_write(phydev, 0x12, 0x2f);
426 - __phy_write(phydev, 0x10, 0x8fae);
427 - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
428 + mtk_tr_modify(phydev, 0x1, 0xf, 0x17, SLAVE_DSP_READY_TIME_MASK,
429 + FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x5e));
430
431 /* Adjust 100_mse_threshold */
432 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
433 -
434 - /* Disable mcc */
435 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
436 + phy_modify_mmd(phydev, MDIO_MMD_VEND1,
437 + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123,
438 + MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK |
439 + MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
440 + FIELD_PREP(MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK,
441 + 0xff) |
442 + FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
443 + 0xff));
444 +
445 + /* If echo time is narrower than 0x3, it will be regarded as noise */
446 + phy_modify_mmd(phydev, MDIO_MMD_VEND1,
447 + MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL,
448 + MTK_MCC_NEARECHO_OFFSET_MASK,
449 + FIELD_PREP(MTK_MCC_NEARECHO_OFFSET_MASK, 0x3));
450 }
451
452 static int mt7530_phy_config_init(struct phy_device *phydev)
453 @@ -48,7 +79,8 @@ static int mt7530_phy_config_init(struct
454 mtk_gephy_config_init(phydev);
455
456 /* Increase post_update_timer */
457 - phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
458 + phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3,
459 + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11, 0x4b);
460
461 return 0;
462 }
463 @@ -89,11 +121,19 @@ static int mt7531_phy_config_init(struct
464
465 /* PHY link down power saving enable */
466 phy_set_bits(phydev, 0x17, BIT(4));
467 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
468 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
469 + MTK_PHY_DA_AD_BUF_BIAS_LP_MASK,
470 + FIELD_PREP(MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3));
471
472 /* Set TX Pair delay selection */
473 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
474 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
475 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_GBE_MODE_TX_DELAY_SEL,
476 + MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
477 + FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
478 + FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
479 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TEST_MODE_TX_DELAY_SEL,
480 + MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
481 + FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
482 + FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
483
484 /* LED Config*/
485 mt7530_led_config_of(phydev);
486 --- a/drivers/net/phy/mediatek/mtk-phy-lib.c
487 +++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
488 @@ -6,6 +6,97 @@
489
490 #include "mtk.h"
491
492 +/* Difference between functions with mtk_tr* and __mtk_tr* prefixes is
493 + * mtk_tr* functions: wrapped by page switching operations
494 + * __mtk_tr* functions: no page switching operations
495 + */
496 +
497 +static void __mtk_tr_access(struct phy_device *phydev, bool read, u8 ch_addr,
498 + u8 node_addr, u8 data_addr)
499 +{
500 + u16 tr_cmd = BIT(15); /* bit 14 & 0 are reserved */
501 +
502 + if (read)
503 + tr_cmd |= BIT(13);
504 +
505 + tr_cmd |= (((ch_addr & 0x3) << 11) |
506 + ((node_addr & 0xf) << 7) |
507 + ((data_addr & 0x3f) << 1));
508 + dev_dbg(&phydev->mdio.dev, "tr_cmd: 0x%x\n", tr_cmd);
509 + __phy_write(phydev, 0x10, tr_cmd);
510 +}
511 +
512 +static void __mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
513 + u8 data_addr, u16 *tr_high, u16 *tr_low)
514 +{
515 + __mtk_tr_access(phydev, true, ch_addr, node_addr, data_addr);
516 + *tr_low = __phy_read(phydev, 0x11);
517 + *tr_high = __phy_read(phydev, 0x12);
518 + dev_dbg(&phydev->mdio.dev, "tr_high read: 0x%x, tr_low read: 0x%x\n",
519 + *tr_high, *tr_low);
520 +}
521 +
522 +u32 mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
523 + u8 data_addr)
524 +{
525 + u16 tr_high;
526 + u16 tr_low;
527 +
528 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
529 + __mtk_tr_read(phydev, ch_addr, node_addr, data_addr, &tr_high, &tr_low);
530 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
531 +
532 + return (tr_high << 16) | tr_low;
533 +}
534 +EXPORT_SYMBOL_GPL(mtk_tr_read);
535 +
536 +static void __mtk_tr_write(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
537 + u8 data_addr, u32 tr_data)
538 +{
539 + __phy_write(phydev, 0x11, tr_data & 0xffff);
540 + __phy_write(phydev, 0x12, tr_data >> 16);
541 + dev_dbg(&phydev->mdio.dev, "tr_high write: 0x%x, tr_low write: 0x%x\n",
542 + tr_data >> 16, tr_data & 0xffff);
543 + __mtk_tr_access(phydev, false, ch_addr, node_addr, data_addr);
544 +}
545 +
546 +void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
547 + u8 data_addr, u32 mask, u32 set)
548 +{
549 + u32 tr_data;
550 + u16 tr_high;
551 + u16 tr_low;
552 +
553 + __mtk_tr_read(phydev, ch_addr, node_addr, data_addr, &tr_high, &tr_low);
554 + tr_data = (tr_high << 16) | tr_low;
555 + tr_data = (tr_data & ~mask) | set;
556 + __mtk_tr_write(phydev, ch_addr, node_addr, data_addr, tr_data);
557 +}
558 +EXPORT_SYMBOL_GPL(__mtk_tr_modify);
559 +
560 +void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
561 + u8 data_addr, u32 mask, u32 set)
562 +{
563 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
564 + __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, mask, set);
565 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
566 +}
567 +EXPORT_SYMBOL_GPL(mtk_tr_modify);
568 +
569 +void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
570 + u8 data_addr, u32 set)
571 +{
572 + __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, 0, set);
573 +}
574 +EXPORT_SYMBOL_GPL(__mtk_tr_set_bits);
575 +
576 +void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
577 + u8 data_addr, u32 clr)
578 +{
579 + __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, clr, 0);
580 +}
581 +EXPORT_SYMBOL_GPL(__mtk_tr_clr_bits);
582 +
583 int mtk_phy_read_page(struct phy_device *phydev)
584 {
585 return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
586 --- a/drivers/net/phy/mediatek/mtk.h
587 +++ b/drivers/net/phy/mediatek/mtk.h
588 @@ -9,6 +9,8 @@
589 #define _MTK_EPHY_H_
590
591 #define MTK_EXT_PAGE_ACCESS 0x1f
592 +#define MTK_PHY_PAGE_STANDARD 0x0000
593 +#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
594
595 /* Registers on MDIO_MMD_VEND2 */
596 #define MTK_PHY_LED0_ON_CTRL 0x24
597 @@ -62,6 +64,17 @@
598 #define MTK_PHY_LED_STATE_FORCE_BLINK 1
599 #define MTK_PHY_LED_STATE_NETDEV 2
600
601 +u32 mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
602 + u8 data_addr);
603 +void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
604 + u8 data_addr, u32 mask, u32 set);
605 +void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
606 + u8 data_addr, u32 mask, u32 set);
607 +void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
608 + u8 data_addr, u32 set);
609 +void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
610 + u8 data_addr, u32 clr);
611 +
612 int mtk_phy_read_page(struct phy_device *phydev);
613 int mtk_phy_write_page(struct phy_device *phydev, int page);
614
Mirror of https://github.com/openwrt/openwrt.git