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1 From 71d88c7409b91c853d7f9c933f5e27933d656e5e Mon Sep 17 00:00:00 2001
2 From: "SkyLake.Huang" <skylake.huang@mediatek.com>
3 Date: Sat, 9 Nov 2024 00:34:52 +0800
4 Subject: [PATCH 05/20] net: phy: mediatek: Move LED helper functions into mtk
5 phy lib
6
7 This patch creates mtk-phy-lib.c & mtk-phy.h and integrates mtk-ge-soc.c's
8 LED helper functions so that we can use those helper functions in other
9 MTK's ethernet phy driver.
10
11 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
12 Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
13 Signed-off-by: David S. Miller <davem@davemloft.net>
14 ---
15 MAINTAINERS | 2 +
16 drivers/net/phy/mediatek/Kconfig | 4 +
17 drivers/net/phy/mediatek/Makefile | 1 +
18 drivers/net/phy/mediatek/mtk-ge-soc.c | 280 +++----------------------
19 drivers/net/phy/mediatek/mtk-phy-lib.c | 254 ++++++++++++++++++++++
20 drivers/net/phy/mediatek/mtk.h | 86 ++++++++
21 6 files changed, 372 insertions(+), 255 deletions(-)
22 create mode 100644 drivers/net/phy/mediatek/mtk-phy-lib.c
23 create mode 100644 drivers/net/phy/mediatek/mtk.h
24
25 --- a/MAINTAINERS
26 +++ b/MAINTAINERS
27 @@ -14428,7 +14428,9 @@ M: SkyLake Huang <SkyLake.Huang@mediatek
28 L: netdev@vger.kernel.org
29 S: Maintained
30 F: drivers/net/phy/mediatek/mtk-ge-soc.c
31 +F: drivers/net/phy/mediatek/mtk-phy-lib.c
32 F: drivers/net/phy/mediatek/mtk-ge.c
33 +F: drivers/net/phy/mediatek/mtk.h
34 F: drivers/phy/mediatek/phy-mtk-xfi-tphy.c
35
36 MEDIATEK I2C CONTROLLER DRIVER
37 --- a/drivers/net/phy/mediatek/Kconfig
38 +++ b/drivers/net/phy/mediatek/Kconfig
39 @@ -1,4 +1,7 @@
40 # SPDX-License-Identifier: GPL-2.0-only
41 +config MTK_NET_PHYLIB
42 + tristate
43 +
44 config MEDIATEK_GE_PHY
45 tristate "MediaTek Gigabit Ethernet PHYs"
46 help
47 @@ -13,6 +16,7 @@ config MEDIATEK_GE_SOC_PHY
48 tristate "MediaTek SoC Ethernet PHYs"
49 depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
50 depends on NVMEM_MTK_EFUSE
51 + select MTK_NET_PHYLIB
52 help
53 Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
54
55 --- a/drivers/net/phy/mediatek/Makefile
56 +++ b/drivers/net/phy/mediatek/Makefile
57 @@ -1,3 +1,4 @@
58 # SPDX-License-Identifier: GPL-2.0
59 +obj-$(CONFIG_MTK_NET_PHYLIB) += mtk-phy-lib.o
60 obj-$(CONFIG_MEDIATEK_GE_PHY) += mtk-ge.o
61 obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mtk-ge-soc.o
62 --- a/drivers/net/phy/mediatek/mtk-ge-soc.c
63 +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
64 @@ -8,6 +8,8 @@
65 #include <linux/phy.h>
66 #include <linux/regmap.h>
67
68 +#include "mtk.h"
69 +
70 #define MTK_GPHY_ID_MT7981 0x03a29461
71 #define MTK_GPHY_ID_MT7988 0x03a29481
72
73 @@ -210,41 +212,6 @@
74 #define MTK_PHY_DA_TX_R50_PAIR_D 0x540
75
76 /* Registers on MDIO_MMD_VEND2 */
77 -#define MTK_PHY_LED0_ON_CTRL 0x24
78 -#define MTK_PHY_LED1_ON_CTRL 0x26
79 -#define MTK_PHY_LED_ON_MASK GENMASK(6, 0)
80 -#define MTK_PHY_LED_ON_LINK1000 BIT(0)
81 -#define MTK_PHY_LED_ON_LINK100 BIT(1)
82 -#define MTK_PHY_LED_ON_LINK10 BIT(2)
83 -#define MTK_PHY_LED_ON_LINK (MTK_PHY_LED_ON_LINK10 |\
84 - MTK_PHY_LED_ON_LINK100 |\
85 - MTK_PHY_LED_ON_LINK1000)
86 -#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
87 -#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
88 -#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
89 -#define MTK_PHY_LED_ON_FORCE_ON BIT(6)
90 -#define MTK_PHY_LED_ON_POLARITY BIT(14)
91 -#define MTK_PHY_LED_ON_ENABLE BIT(15)
92 -
93 -#define MTK_PHY_LED0_BLINK_CTRL 0x25
94 -#define MTK_PHY_LED1_BLINK_CTRL 0x27
95 -#define MTK_PHY_LED_BLINK_1000TX BIT(0)
96 -#define MTK_PHY_LED_BLINK_1000RX BIT(1)
97 -#define MTK_PHY_LED_BLINK_100TX BIT(2)
98 -#define MTK_PHY_LED_BLINK_100RX BIT(3)
99 -#define MTK_PHY_LED_BLINK_10TX BIT(4)
100 -#define MTK_PHY_LED_BLINK_10RX BIT(5)
101 -#define MTK_PHY_LED_BLINK_RX (MTK_PHY_LED_BLINK_10RX |\
102 - MTK_PHY_LED_BLINK_100RX |\
103 - MTK_PHY_LED_BLINK_1000RX)
104 -#define MTK_PHY_LED_BLINK_TX (MTK_PHY_LED_BLINK_10TX |\
105 - MTK_PHY_LED_BLINK_100TX |\
106 - MTK_PHY_LED_BLINK_1000TX)
107 -#define MTK_PHY_LED_BLINK_COLLISION BIT(6)
108 -#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
109 -#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
110 -#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9)
111 -
112 #define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1)
113
114 #define MTK_PHY_RG_BG_RASEL 0x115
115 @@ -299,14 +266,6 @@ enum CAL_MODE {
116 SW_M
117 };
118
119 -#define MTK_PHY_LED_STATE_FORCE_ON 0
120 -#define MTK_PHY_LED_STATE_FORCE_BLINK 1
121 -#define MTK_PHY_LED_STATE_NETDEV 2
122 -
123 -struct mtk_socphy_priv {
124 - unsigned long led_state;
125 -};
126 -
127 struct mtk_socphy_shared {
128 u32 boottrap;
129 struct mtk_socphy_priv priv[4];
130 @@ -1172,76 +1131,23 @@ static int mt798x_phy_config_init(struct
131 return mt798x_phy_calibration(phydev);
132 }
133
134 -static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
135 - bool on)
136 -{
137 - unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
138 - struct mtk_socphy_priv *priv = phydev->priv;
139 - bool changed;
140 -
141 - if (on)
142 - changed = !test_and_set_bit(bit_on, &priv->led_state);
143 - else
144 - changed = !!test_and_clear_bit(bit_on, &priv->led_state);
145 -
146 - changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV +
147 - (index ? 16 : 0), &priv->led_state);
148 - if (changed)
149 - return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
150 - MTK_PHY_LED1_ON_CTRL :
151 - MTK_PHY_LED0_ON_CTRL,
152 - MTK_PHY_LED_ON_MASK,
153 - on ? MTK_PHY_LED_ON_FORCE_ON : 0);
154 - else
155 - return 0;
156 -}
157 -
158 -static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
159 - bool blinking)
160 -{
161 - unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
162 - (index ? 16 : 0);
163 - struct mtk_socphy_priv *priv = phydev->priv;
164 - bool changed;
165 -
166 - if (blinking)
167 - changed = !test_and_set_bit(bit_blink, &priv->led_state);
168 - else
169 - changed = !!test_and_clear_bit(bit_blink, &priv->led_state);
170 -
171 - changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV +
172 - (index ? 16 : 0), &priv->led_state);
173 - if (changed)
174 - return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
175 - MTK_PHY_LED1_BLINK_CTRL :
176 - MTK_PHY_LED0_BLINK_CTRL,
177 - blinking ?
178 - MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
179 - else
180 - return 0;
181 -}
182 -
183 static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
184 unsigned long *delay_on,
185 unsigned long *delay_off)
186 {
187 bool blinking = false;
188 - int err = 0;
189 -
190 - if (index > 1)
191 - return -EINVAL;
192 + int err;
193
194 - if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
195 - blinking = true;
196 - *delay_on = 50;
197 - *delay_off = 50;
198 - }
199 + err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking);
200 + if (err < 0)
201 + return err;
202
203 - err = mt798x_phy_hw_led_blink_set(phydev, index, blinking);
204 + err = mtk_phy_hw_led_blink_set(phydev, index, blinking);
205 if (err)
206 return err;
207
208 - return mt798x_phy_hw_led_on_set(phydev, index, false);
209 + return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK,
210 + false);
211 }
212
213 static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
214 @@ -1249,11 +1155,12 @@ static int mt798x_phy_led_brightness_set
215 {
216 int err;
217
218 - err = mt798x_phy_hw_led_blink_set(phydev, index, false);
219 + err = mtk_phy_hw_led_blink_set(phydev, index, false);
220 if (err)
221 return err;
222
223 - return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF));
224 + return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK,
225 + (value != LED_OFF));
226 }
227
228 static const unsigned long supported_triggers =
229 @@ -1269,155 +1176,26 @@ static const unsigned long supported_tri
230 static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
231 unsigned long rules)
232 {
233 - if (index > 1)
234 - return -EINVAL;
235 -
236 - /* All combinations of the supported triggers are allowed */
237 - if (rules & ~supported_triggers)
238 - return -EOPNOTSUPP;
239 -
240 - return 0;
241 -};
242 + return mtk_phy_led_hw_is_supported(phydev, index, rules,
243 + supported_triggers);
244 +}
245
246 static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
247 unsigned long *rules)
248 {
249 - unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
250 - (index ? 16 : 0);
251 - unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
252 - unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
253 - struct mtk_socphy_priv *priv = phydev->priv;
254 - int on, blink;
255 -
256 - if (index > 1)
257 - return -EINVAL;
258 -
259 - on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
260 - index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL);
261 -
262 - if (on < 0)
263 - return -EIO;
264 -
265 - blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
266 - index ? MTK_PHY_LED1_BLINK_CTRL :
267 - MTK_PHY_LED0_BLINK_CTRL);
268 - if (blink < 0)
269 - return -EIO;
270 -
271 - if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX |
272 - MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) ||
273 - (blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX)))
274 - set_bit(bit_netdev, &priv->led_state);
275 - else
276 - clear_bit(bit_netdev, &priv->led_state);
277 -
278 - if (on & MTK_PHY_LED_ON_FORCE_ON)
279 - set_bit(bit_on, &priv->led_state);
280 - else
281 - clear_bit(bit_on, &priv->led_state);
282 -
283 - if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK)
284 - set_bit(bit_blink, &priv->led_state);
285 - else
286 - clear_bit(bit_blink, &priv->led_state);
287 -
288 - if (!rules)
289 - return 0;
290 -
291 - if (on & MTK_PHY_LED_ON_LINK)
292 - *rules |= BIT(TRIGGER_NETDEV_LINK);
293 -
294 - if (on & MTK_PHY_LED_ON_LINK10)
295 - *rules |= BIT(TRIGGER_NETDEV_LINK_10);
296 -
297 - if (on & MTK_PHY_LED_ON_LINK100)
298 - *rules |= BIT(TRIGGER_NETDEV_LINK_100);
299 -
300 - if (on & MTK_PHY_LED_ON_LINK1000)
301 - *rules |= BIT(TRIGGER_NETDEV_LINK_1000);
302 -
303 - if (on & MTK_PHY_LED_ON_FDX)
304 - *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
305 -
306 - if (on & MTK_PHY_LED_ON_HDX)
307 - *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
308 -
309 - if (blink & MTK_PHY_LED_BLINK_RX)
310 - *rules |= BIT(TRIGGER_NETDEV_RX);
311 -
312 - if (blink & MTK_PHY_LED_BLINK_TX)
313 - *rules |= BIT(TRIGGER_NETDEV_TX);
314 -
315 - return 0;
316 + return mtk_phy_led_hw_ctrl_get(phydev, index, rules,
317 + MTK_GPHY_LED_ON_SET,
318 + MTK_GPHY_LED_RX_BLINK_SET,
319 + MTK_GPHY_LED_TX_BLINK_SET);
320 };
321
322 static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
323 unsigned long rules)
324 {
325 - unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
326 - struct mtk_socphy_priv *priv = phydev->priv;
327 - u16 on = 0, blink = 0;
328 - int ret;
329 -
330 - if (index > 1)
331 - return -EINVAL;
332 -
333 - if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
334 - on |= MTK_PHY_LED_ON_FDX;
335 -
336 - if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
337 - on |= MTK_PHY_LED_ON_HDX;
338 -
339 - if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
340 - on |= MTK_PHY_LED_ON_LINK10;
341 -
342 - if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
343 - on |= MTK_PHY_LED_ON_LINK100;
344 -
345 - if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
346 - on |= MTK_PHY_LED_ON_LINK1000;
347 -
348 - if (rules & BIT(TRIGGER_NETDEV_RX)) {
349 - blink |= (on & MTK_PHY_LED_ON_LINK) ?
350 - (((on & MTK_PHY_LED_ON_LINK10) ?
351 - MTK_PHY_LED_BLINK_10RX : 0) |
352 - ((on & MTK_PHY_LED_ON_LINK100) ?
353 - MTK_PHY_LED_BLINK_100RX : 0) |
354 - ((on & MTK_PHY_LED_ON_LINK1000) ?
355 - MTK_PHY_LED_BLINK_1000RX : 0)) :
356 - MTK_PHY_LED_BLINK_RX;
357 - }
358 -
359 - if (rules & BIT(TRIGGER_NETDEV_TX)) {
360 - blink |= (on & MTK_PHY_LED_ON_LINK) ?
361 - (((on & MTK_PHY_LED_ON_LINK10) ?
362 - MTK_PHY_LED_BLINK_10TX : 0) |
363 - ((on & MTK_PHY_LED_ON_LINK100) ?
364 - MTK_PHY_LED_BLINK_100TX : 0) |
365 - ((on & MTK_PHY_LED_ON_LINK1000) ?
366 - MTK_PHY_LED_BLINK_1000TX : 0)) :
367 - MTK_PHY_LED_BLINK_TX;
368 - }
369 -
370 - if (blink || on)
371 - set_bit(bit_netdev, &priv->led_state);
372 - else
373 - clear_bit(bit_netdev, &priv->led_state);
374 -
375 - ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
376 - MTK_PHY_LED1_ON_CTRL :
377 - MTK_PHY_LED0_ON_CTRL,
378 - MTK_PHY_LED_ON_FDX |
379 - MTK_PHY_LED_ON_HDX |
380 - MTK_PHY_LED_ON_LINK,
381 - on);
382 -
383 - if (ret)
384 - return ret;
385 -
386 - return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
387 - MTK_PHY_LED1_BLINK_CTRL :
388 - MTK_PHY_LED0_BLINK_CTRL, blink);
389 + return mtk_phy_led_hw_ctrl_set(phydev, index, rules,
390 + MTK_GPHY_LED_ON_SET,
391 + MTK_GPHY_LED_RX_BLINK_SET,
392 + MTK_GPHY_LED_TX_BLINK_SET);
393 };
394
395 static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num)
396 @@ -1492,14 +1270,6 @@ static int mt7988_phy_probe_shared(struc
397 return 0;
398 }
399
400 -static void mt798x_phy_leds_state_init(struct phy_device *phydev)
401 -{
402 - int i;
403 -
404 - for (i = 0; i < 2; ++i)
405 - mt798x_phy_led_hw_control_get(phydev, i, NULL);
406 -}
407 -
408 static int mt7988_phy_probe(struct phy_device *phydev)
409 {
410 struct mtk_socphy_shared *shared;
411 @@ -1525,7 +1295,7 @@ static int mt7988_phy_probe(struct phy_d
412
413 phydev->priv = priv;
414
415 - mt798x_phy_leds_state_init(phydev);
416 + mtk_phy_leds_state_init(phydev);
417
418 err = mt7988_phy_fix_leds_polarities(phydev);
419 if (err)
420 @@ -1552,7 +1322,7 @@ static int mt7981_phy_probe(struct phy_d
421
422 phydev->priv = priv;
423
424 - mt798x_phy_leds_state_init(phydev);
425 + mtk_phy_leds_state_init(phydev);
426
427 return mt798x_phy_calibration(phydev);
428 }
429 --- /dev/null
430 +++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
431 @@ -0,0 +1,254 @@
432 +// SPDX-License-Identifier: GPL-2.0
433 +#include <linux/phy.h>
434 +#include <linux/module.h>
435 +
436 +#include <linux/netdevice.h>
437 +
438 +#include "mtk.h"
439 +
440 +int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
441 + unsigned long rules,
442 + unsigned long supported_triggers)
443 +{
444 + if (index > 1)
445 + return -EINVAL;
446 +
447 + /* All combinations of the supported triggers are allowed */
448 + if (rules & ~supported_triggers)
449 + return -EOPNOTSUPP;
450 +
451 + return 0;
452 +}
453 +EXPORT_SYMBOL_GPL(mtk_phy_led_hw_is_supported);
454 +
455 +int mtk_phy_led_hw_ctrl_get(struct phy_device *phydev, u8 index,
456 + unsigned long *rules, u16 on_set,
457 + u16 rx_blink_set, u16 tx_blink_set)
458 +{
459 + unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
460 + (index ? 16 : 0);
461 + unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
462 + unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
463 + struct mtk_socphy_priv *priv = phydev->priv;
464 + int on, blink;
465 +
466 + if (index > 1)
467 + return -EINVAL;
468 +
469 + on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
470 + index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL);
471 +
472 + if (on < 0)
473 + return -EIO;
474 +
475 + blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
476 + index ? MTK_PHY_LED1_BLINK_CTRL :
477 + MTK_PHY_LED0_BLINK_CTRL);
478 + if (blink < 0)
479 + return -EIO;
480 +
481 + if ((on & (on_set | MTK_PHY_LED_ON_FDX |
482 + MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) ||
483 + (blink & (rx_blink_set | tx_blink_set)))
484 + set_bit(bit_netdev, &priv->led_state);
485 + else
486 + clear_bit(bit_netdev, &priv->led_state);
487 +
488 + if (on & MTK_PHY_LED_ON_FORCE_ON)
489 + set_bit(bit_on, &priv->led_state);
490 + else
491 + clear_bit(bit_on, &priv->led_state);
492 +
493 + if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK)
494 + set_bit(bit_blink, &priv->led_state);
495 + else
496 + clear_bit(bit_blink, &priv->led_state);
497 +
498 + if (!rules)
499 + return 0;
500 +
501 + if (on & on_set)
502 + *rules |= BIT(TRIGGER_NETDEV_LINK);
503 +
504 + if (on & MTK_PHY_LED_ON_LINK10)
505 + *rules |= BIT(TRIGGER_NETDEV_LINK_10);
506 +
507 + if (on & MTK_PHY_LED_ON_LINK100)
508 + *rules |= BIT(TRIGGER_NETDEV_LINK_100);
509 +
510 + if (on & MTK_PHY_LED_ON_LINK1000)
511 + *rules |= BIT(TRIGGER_NETDEV_LINK_1000);
512 +
513 + if (on & MTK_PHY_LED_ON_LINK2500)
514 + *rules |= BIT(TRIGGER_NETDEV_LINK_2500);
515 +
516 + if (on & MTK_PHY_LED_ON_FDX)
517 + *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
518 +
519 + if (on & MTK_PHY_LED_ON_HDX)
520 + *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
521 +
522 + if (blink & rx_blink_set)
523 + *rules |= BIT(TRIGGER_NETDEV_RX);
524 +
525 + if (blink & tx_blink_set)
526 + *rules |= BIT(TRIGGER_NETDEV_TX);
527 +
528 + return 0;
529 +}
530 +EXPORT_SYMBOL_GPL(mtk_phy_led_hw_ctrl_get);
531 +
532 +int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index,
533 + unsigned long rules, u16 on_set,
534 + u16 rx_blink_set, u16 tx_blink_set)
535 +{
536 + unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
537 + struct mtk_socphy_priv *priv = phydev->priv;
538 + u16 on = 0, blink = 0;
539 + int ret;
540 +
541 + if (index > 1)
542 + return -EINVAL;
543 +
544 + if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
545 + on |= MTK_PHY_LED_ON_FDX;
546 +
547 + if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
548 + on |= MTK_PHY_LED_ON_HDX;
549 +
550 + if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
551 + on |= MTK_PHY_LED_ON_LINK10;
552 +
553 + if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
554 + on |= MTK_PHY_LED_ON_LINK100;
555 +
556 + if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
557 + on |= MTK_PHY_LED_ON_LINK1000;
558 +
559 + if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK)))
560 + on |= MTK_PHY_LED_ON_LINK2500;
561 +
562 + if (rules & BIT(TRIGGER_NETDEV_RX)) {
563 + blink |= (on & on_set) ?
564 + (((on & MTK_PHY_LED_ON_LINK10) ?
565 + MTK_PHY_LED_BLINK_10RX : 0) |
566 + ((on & MTK_PHY_LED_ON_LINK100) ?
567 + MTK_PHY_LED_BLINK_100RX : 0) |
568 + ((on & MTK_PHY_LED_ON_LINK1000) ?
569 + MTK_PHY_LED_BLINK_1000RX : 0) |
570 + ((on & MTK_PHY_LED_ON_LINK2500) ?
571 + MTK_PHY_LED_BLINK_2500RX : 0)) :
572 + rx_blink_set;
573 + }
574 +
575 + if (rules & BIT(TRIGGER_NETDEV_TX)) {
576 + blink |= (on & on_set) ?
577 + (((on & MTK_PHY_LED_ON_LINK10) ?
578 + MTK_PHY_LED_BLINK_10TX : 0) |
579 + ((on & MTK_PHY_LED_ON_LINK100) ?
580 + MTK_PHY_LED_BLINK_100TX : 0) |
581 + ((on & MTK_PHY_LED_ON_LINK1000) ?
582 + MTK_PHY_LED_BLINK_1000TX : 0) |
583 + ((on & MTK_PHY_LED_ON_LINK2500) ?
584 + MTK_PHY_LED_BLINK_2500TX : 0)) :
585 + tx_blink_set;
586 + }
587 +
588 + if (blink || on)
589 + set_bit(bit_netdev, &priv->led_state);
590 + else
591 + clear_bit(bit_netdev, &priv->led_state);
592 +
593 + ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
594 + MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
595 + MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX | on_set,
596 + on);
597 +
598 + if (ret)
599 + return ret;
600 +
601 + return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
602 + MTK_PHY_LED1_BLINK_CTRL :
603 + MTK_PHY_LED0_BLINK_CTRL, blink);
604 +}
605 +EXPORT_SYMBOL_GPL(mtk_phy_led_hw_ctrl_set);
606 +
607 +int mtk_phy_led_num_dly_cfg(u8 index, unsigned long *delay_on,
608 + unsigned long *delay_off, bool *blinking)
609 +{
610 + if (index > 1)
611 + return -EINVAL;
612 +
613 + if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
614 + *blinking = true;
615 + *delay_on = 50;
616 + *delay_off = 50;
617 + }
618 +
619 + return 0;
620 +}
621 +EXPORT_SYMBOL_GPL(mtk_phy_led_num_dly_cfg);
622 +
623 +int mtk_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
624 + u16 led_on_mask, bool on)
625 +{
626 + unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
627 + struct mtk_socphy_priv *priv = phydev->priv;
628 + bool changed;
629 +
630 + if (on)
631 + changed = !test_and_set_bit(bit_on, &priv->led_state);
632 + else
633 + changed = !!test_and_clear_bit(bit_on, &priv->led_state);
634 +
635 + changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV +
636 + (index ? 16 : 0), &priv->led_state);
637 + if (changed)
638 + return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
639 + MTK_PHY_LED1_ON_CTRL :
640 + MTK_PHY_LED0_ON_CTRL,
641 + led_on_mask,
642 + on ? MTK_PHY_LED_ON_FORCE_ON : 0);
643 + else
644 + return 0;
645 +}
646 +EXPORT_SYMBOL_GPL(mtk_phy_hw_led_on_set);
647 +
648 +int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, bool blinking)
649 +{
650 + unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
651 + (index ? 16 : 0);
652 + struct mtk_socphy_priv *priv = phydev->priv;
653 + bool changed;
654 +
655 + if (blinking)
656 + changed = !test_and_set_bit(bit_blink, &priv->led_state);
657 + else
658 + changed = !!test_and_clear_bit(bit_blink, &priv->led_state);
659 +
660 + changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV +
661 + (index ? 16 : 0), &priv->led_state);
662 + if (changed)
663 + return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
664 + MTK_PHY_LED1_BLINK_CTRL :
665 + MTK_PHY_LED0_BLINK_CTRL,
666 + blinking ?
667 + MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
668 + else
669 + return 0;
670 +}
671 +EXPORT_SYMBOL_GPL(mtk_phy_hw_led_blink_set);
672 +
673 +void mtk_phy_leds_state_init(struct phy_device *phydev)
674 +{
675 + int i;
676 +
677 + for (i = 0; i < 2; ++i)
678 + phydev->drv->led_hw_control_get(phydev, i, NULL);
679 +}
680 +EXPORT_SYMBOL_GPL(mtk_phy_leds_state_init);
681 +
682 +MODULE_DESCRIPTION("MediaTek Ethernet PHY driver common");
683 +MODULE_AUTHOR("Sky Huang <SkyLake.Huang@mediatek.com>");
684 +MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
685 +MODULE_LICENSE("GPL");
686 --- /dev/null
687 +++ b/drivers/net/phy/mediatek/mtk.h
688 @@ -0,0 +1,86 @@
689 +/* SPDX-License-Identifier: GPL-2.0
690 + *
691 + * Common definition for Mediatek Ethernet PHYs
692 + * Author: SkyLake Huang <SkyLake.Huang@mediatek.com>
693 + * Copyright (c) 2024 MediaTek Inc.
694 + */
695 +
696 +#ifndef _MTK_EPHY_H_
697 +#define _MTK_EPHY_H_
698 +
699 +#define MTK_EXT_PAGE_ACCESS 0x1f
700 +
701 +/* Registers on MDIO_MMD_VEND2 */
702 +#define MTK_PHY_LED0_ON_CTRL 0x24
703 +#define MTK_PHY_LED1_ON_CTRL 0x26
704 +#define MTK_GPHY_LED_ON_MASK GENMASK(6, 0)
705 +#define MTK_2P5GPHY_LED_ON_MASK GENMASK(7, 0)
706 +#define MTK_PHY_LED_ON_LINK1000 BIT(0)
707 +#define MTK_PHY_LED_ON_LINK100 BIT(1)
708 +#define MTK_PHY_LED_ON_LINK10 BIT(2)
709 +#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
710 +#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
711 +#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
712 +#define MTK_PHY_LED_ON_FORCE_ON BIT(6)
713 +#define MTK_PHY_LED_ON_LINK2500 BIT(7)
714 +#define MTK_PHY_LED_ON_POLARITY BIT(14)
715 +#define MTK_PHY_LED_ON_ENABLE BIT(15)
716 +
717 +#define MTK_PHY_LED0_BLINK_CTRL 0x25
718 +#define MTK_PHY_LED1_BLINK_CTRL 0x27
719 +#define MTK_PHY_LED_BLINK_1000TX BIT(0)
720 +#define MTK_PHY_LED_BLINK_1000RX BIT(1)
721 +#define MTK_PHY_LED_BLINK_100TX BIT(2)
722 +#define MTK_PHY_LED_BLINK_100RX BIT(3)
723 +#define MTK_PHY_LED_BLINK_10TX BIT(4)
724 +#define MTK_PHY_LED_BLINK_10RX BIT(5)
725 +#define MTK_PHY_LED_BLINK_COLLISION BIT(6)
726 +#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
727 +#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
728 +#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9)
729 +#define MTK_PHY_LED_BLINK_2500TX BIT(10)
730 +#define MTK_PHY_LED_BLINK_2500RX BIT(11)
731 +
732 +#define MTK_GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK1000 | \
733 + MTK_PHY_LED_ON_LINK100 | \
734 + MTK_PHY_LED_ON_LINK10)
735 +#define MTK_GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \
736 + MTK_PHY_LED_BLINK_100RX | \
737 + MTK_PHY_LED_BLINK_10RX)
738 +#define MTK_GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \
739 + MTK_PHY_LED_BLINK_100RX | \
740 + MTK_PHY_LED_BLINK_10RX)
741 +
742 +#define MTK_2P5GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK2500 | \
743 + MTK_GPHY_LED_ON_SET)
744 +#define MTK_2P5GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \
745 + MTK_GPHY_LED_RX_BLINK_SET)
746 +#define MTK_2P5GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \
747 + MTK_GPHY_LED_TX_BLINK_SET)
748 +
749 +#define MTK_PHY_LED_STATE_FORCE_ON 0
750 +#define MTK_PHY_LED_STATE_FORCE_BLINK 1
751 +#define MTK_PHY_LED_STATE_NETDEV 2
752 +
753 +struct mtk_socphy_priv {
754 + unsigned long led_state;
755 +};
756 +
757 +int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
758 + unsigned long rules,
759 + unsigned long supported_triggers);
760 +int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index,
761 + unsigned long rules, u16 on_set,
762 + u16 rx_blink_set, u16 tx_blink_set);
763 +int mtk_phy_led_hw_ctrl_get(struct phy_device *phydev, u8 index,
764 + unsigned long *rules, u16 on_set,
765 + u16 rx_blink_set, u16 tx_blink_set);
766 +int mtk_phy_led_num_dly_cfg(u8 index, unsigned long *delay_on,
767 + unsigned long *delay_off, bool *blinking);
768 +int mtk_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
769 + u16 led_on_mask, bool on);
770 +int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
771 + bool blinking);
772 +void mtk_phy_leds_state_init(struct phy_device *phydev);
773 +
774 +#endif /* _MTK_EPHY_H_ */
Mirror of https://github.com/openwrt/openwrt.git