git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From 980136d1c2b95644b96df6c7ec00ca5d7c87f37f Mon Sep 17 00:00:00 2001
   2 From: Krishna chaitanya chundru <quic_krichai@quicinc.com>
   3 Date: Wed, 19 Jun 2024 20:41:10 +0530
   4 Subject: [PATCH] PCI: qcom: Add ICC bandwidth vote for CPU to PCIe path
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   8
   9 To access the host controller registers of the host controller and the
  10 endpoint BAR/config space, the CPU-PCIe ICC (interconnect) path should
  11 be voted otherwise it may lead to NoC (Network on chip) timeout.
  12 We are surviving because of other driver voting for this path.
  13
  14 As there is less access on this path compared to PCIe to mem path
  15 add minimum vote i.e 1KBps bandwidth always which is sufficient enough
  16 to keep the path active and is recommended by HW team.
  17
  18 During S2RAM (Suspend-to-RAM), the DBI access can happen very late (while
  19 disabling the boot CPU). So do not disable the CPU-PCIe interconnect path
  20 during S2RAM as that may lead to NoC error.
  21
  22 Link: https://lore.kernel.org/linux-pci/20240619-opp_support-v15-1-aa769a2173a3@quicinc.com
  23 Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
  24 Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
  25 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  26 Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
  27 Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  28 ---
  29  drivers/pci/controller/dwc/pcie-qcom.c | 45 +++++++++++++++++++++++++++++++---
  30  1 file changed, 41 insertions(+), 4 deletions(-)
  31
  32 --- a/drivers/pci/controller/dwc/pcie-qcom.c
  33 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
  34 @@ -245,6 +245,7 @@ struct qcom_pcie {
  35         struct phy *phy;
  36         struct gpio_desc *reset;
  37         struct icc_path *icc_mem;
  38 +       struct icc_path *icc_cpu;
  39         const struct qcom_pcie_cfg *cfg;
  40         struct dentry *debugfs;
  41         bool suspended;
  42 @@ -1357,6 +1358,9 @@ static int qcom_pcie_icc_init(struct qco
  43         if (IS_ERR(pcie->icc_mem))
  44                 return PTR_ERR(pcie->icc_mem);
  45
  46 +       pcie->icc_cpu = devm_of_icc_get(pci->dev, "cpu-pcie");
  47 +       if (IS_ERR(pcie->icc_cpu))
  48 +               return PTR_ERR(pcie->icc_cpu);
  49         /*
  50          * Some Qualcomm platforms require interconnect bandwidth constraints
  51          * to be set before enabling interconnect clocks.
  52 @@ -1366,11 +1370,25 @@ static int qcom_pcie_icc_init(struct qco
  53          */
  54         ret = icc_set_bw(pcie->icc_mem, 0, MBps_to_icc(250));
  55         if (ret) {
  56 -               dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
  57 +               dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n",
  58                         ret);
  59                 return ret;
  60         }
  61
  62 +       /*
  63 +        * Since the CPU-PCIe path is only used for activities like register
  64 +        * access of the host controller and endpoint Config/BAR space access,
  65 +        * HW team has recommended to use a minimal bandwidth of 1KBps just to
  66 +        * keep the path active.
  67 +        */
  68 +       ret = icc_set_bw(pcie->icc_cpu, 0, kBps_to_icc(1));
  69 +       if (ret) {
  70 +               dev_err(pci->dev, "Failed to set bandwidth for CPU-PCIe interconnect path: %d\n",
  71 +                       ret);
  72 +               icc_set_bw(pcie->icc_mem, 0, 0);
  73 +               return ret;
  74 +       }
  75 +
  76         return 0;
  77  }
  78
  79 @@ -1411,7 +1429,7 @@ static void qcom_pcie_icc_update(struct
  80
  81         ret = icc_set_bw(pcie->icc_mem, 0, width * bw);
  82         if (ret) {
  83 -               dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
  84 +               dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n",
  85                         ret);
  86         }
  87  }
  88 @@ -1573,7 +1591,7 @@ static int qcom_pcie_suspend_noirq(struc
  89          */
  90         ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1));
  91         if (ret) {
  92 -               dev_err(dev, "Failed to set interconnect bandwidth: %d\n", ret);
  93 +               dev_err(dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", ret);
  94                 return ret;
  95         }
  96
  97 @@ -1597,7 +1615,18 @@ static int qcom_pcie_suspend_noirq(struc
  98                 pcie->suspended = true;
  99         }
 100
 101 -       return 0;
 102 +       /*
 103 +        * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM.
 104 +        * Because on some platforms, DBI access can happen very late during the
 105 +        * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC
 106 +        * error.
 107 +        */
 108 +       if (pm_suspend_target_state != PM_SUSPEND_MEM) {
 109 +               ret = icc_disable(pcie->icc_cpu);
 110 +               if (ret)
 111 +                       dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret);
 112 +       }
 113 +       return ret;
 114  }
 115
 116  static int qcom_pcie_resume_noirq(struct device *dev)
 117 @@ -1605,6 +1634,14 @@ static int qcom_pcie_resume_noirq(struct
 118         struct qcom_pcie *pcie = dev_get_drvdata(dev);
 119         int ret;
 120
 121 +       if (pm_suspend_target_state != PM_SUSPEND_MEM) {
 122 +               ret = icc_enable(pcie->icc_cpu);
 123 +               if (ret) {
 124 +                       dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret);
 125 +                       return ret;
 126 +               }
 127 +       }
 128 +
 129         if (pcie->suspended) {
 130                 ret = qcom_pcie_host_init(&pcie->pci->pp);
 131                 if (ret)