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1 From 6f8c1ed25809181c187a59b1caaa1521756924bf Mon Sep 17 00:00:00 2001
2 From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 Date: Tue, 22 Oct 2024 17:47:26 +0200
4 Subject: [PATCH] arm64: dts: qcom: ipq: change labels to lower-case
5
6 DTS coding style expects labels to be lowercase. No functional impact.
7 Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).
8
9 Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
10 Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-1-0505bc7d2c56@linaro.org
11 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
12 ---
13 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 +++---
14 arch/arm64/boot/dts/qcom/ipq5332.dtsi | 18 +++++-----
15 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 +++++++-------
16 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 18 +++++-----
17 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 50 +++++++++++++--------------
18 5 files changed, 61 insertions(+), 61 deletions(-)
19
20 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
21 +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
22 @@ -31,27 +31,27 @@
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 - CPU0: cpu@0 {
27 + cpu0: cpu@0 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a53";
30 reg = <0x0>;
31 enable-method = "psci";
32 - next-level-cache = <&L2_0>;
33 + next-level-cache = <&l2_0>;
34 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
35 operating-points-v2 = <&cpu_opp_table>;
36 };
37
38 - CPU1: cpu@1 {
39 + cpu1: cpu@1 {
40 device_type = "cpu";
41 compatible = "arm,cortex-a53";
42 reg = <0x1>;
43 enable-method = "psci";
44 - next-level-cache = <&L2_0>;
45 + next-level-cache = <&l2_0>;
46 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
47 operating-points-v2 = <&cpu_opp_table>;
48 };
49
50 - L2_0: l2-cache {
51 + l2_0: l2-cache {
52 compatible = "cache";
53 cache-level = <2>;
54 cache-size = <0x80000>;
55 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
56 +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
57 @@ -30,47 +30,47 @@
58 #address-cells = <1>;
59 #size-cells = <0>;
60
61 - CPU0: cpu@0 {
62 + cpu0: cpu@0 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a53";
65 reg = <0x0>;
66 enable-method = "psci";
67 - next-level-cache = <&L2_0>;
68 + next-level-cache = <&l2_0>;
69 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
70 operating-points-v2 = <&cpu_opp_table>;
71 };
72
73 - CPU1: cpu@1 {
74 + cpu1: cpu@1 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a53";
77 reg = <0x1>;
78 enable-method = "psci";
79 - next-level-cache = <&L2_0>;
80 + next-level-cache = <&l2_0>;
81 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
82 operating-points-v2 = <&cpu_opp_table>;
83 };
84
85 - CPU2: cpu@2 {
86 + cpu2: cpu@2 {
87 device_type = "cpu";
88 compatible = "arm,cortex-a53";
89 reg = <0x2>;
90 enable-method = "psci";
91 - next-level-cache = <&L2_0>;
92 + next-level-cache = <&l2_0>;
93 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
94 operating-points-v2 = <&cpu_opp_table>;
95 };
96
97 - CPU3: cpu@3 {
98 + cpu3: cpu@3 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a53";
101 reg = <0x3>;
102 enable-method = "psci";
103 - next-level-cache = <&L2_0>;
104 + next-level-cache = <&l2_0>;
105 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
106 operating-points-v2 = <&cpu_opp_table>;
107 };
108
109 - L2_0: l2-cache {
110 + l2_0: l2-cache {
111 compatible = "cache";
112 cache-level = <2>;
113 cache-unified;
114 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
115 +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
116 @@ -34,12 +34,12 @@
117 #address-cells = <1>;
118 #size-cells = <0>;
119
120 - CPU0: cpu@0 {
121 + cpu0: cpu@0 {
122 device_type = "cpu";
123 compatible = "arm,cortex-a53";
124 reg = <0x0>;
125 enable-method = "psci";
126 - next-level-cache = <&L2_0>;
127 + next-level-cache = <&l2_0>;
128 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
129 clock-names = "cpu";
130 operating-points-v2 = <&cpu_opp_table>;
131 @@ -47,12 +47,12 @@
132 #cooling-cells = <2>;
133 };
134
135 - CPU1: cpu@1 {
136 + cpu1: cpu@1 {
137 device_type = "cpu";
138 compatible = "arm,cortex-a53";
139 enable-method = "psci";
140 reg = <0x1>;
141 - next-level-cache = <&L2_0>;
142 + next-level-cache = <&l2_0>;
143 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
144 clock-names = "cpu";
145 operating-points-v2 = <&cpu_opp_table>;
146 @@ -60,12 +60,12 @@
147 #cooling-cells = <2>;
148 };
149
150 - CPU2: cpu@2 {
151 + cpu2: cpu@2 {
152 device_type = "cpu";
153 compatible = "arm,cortex-a53";
154 enable-method = "psci";
155 reg = <0x2>;
156 - next-level-cache = <&L2_0>;
157 + next-level-cache = <&l2_0>;
158 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
159 clock-names = "cpu";
160 operating-points-v2 = <&cpu_opp_table>;
161 @@ -73,12 +73,12 @@
162 #cooling-cells = <2>;
163 };
164
165 - CPU3: cpu@3 {
166 + cpu3: cpu@3 {
167 device_type = "cpu";
168 compatible = "arm,cortex-a53";
169 enable-method = "psci";
170 reg = <0x3>;
171 - next-level-cache = <&L2_0>;
172 + next-level-cache = <&l2_0>;
173 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
174 clock-names = "cpu";
175 operating-points-v2 = <&cpu_opp_table>;
176 @@ -86,7 +86,7 @@
177 #cooling-cells = <2>;
178 };
179
180 - L2_0: l2-cache {
181 + l2_0: l2-cache {
182 compatible = "cache";
183 cache-level = <2>;
184 cache-unified;
185 @@ -993,10 +993,10 @@
186 cooling-maps {
187 map0 {
188 trip = <&cpu_alert>;
189 - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
190 - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
191 - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
192 - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
193 + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
194 + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
195 + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
196 + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
197 };
198 };
199 };
200 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
201 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
202 @@ -32,39 +32,39 @@
203 #address-cells = <1>;
204 #size-cells = <0>;
205
206 - CPU0: cpu@0 {
207 + cpu0: cpu@0 {
208 device_type = "cpu";
209 compatible = "arm,cortex-a53";
210 reg = <0x0>;
211 - next-level-cache = <&L2_0>;
212 + next-level-cache = <&l2_0>;
213 enable-method = "psci";
214 };
215
216 - CPU1: cpu@1 {
217 + cpu1: cpu@1 {
218 device_type = "cpu";
219 compatible = "arm,cortex-a53";
220 enable-method = "psci";
221 reg = <0x1>;
222 - next-level-cache = <&L2_0>;
223 + next-level-cache = <&l2_0>;
224 };
225
226 - CPU2: cpu@2 {
227 + cpu2: cpu@2 {
228 device_type = "cpu";
229 compatible = "arm,cortex-a53";
230 enable-method = "psci";
231 reg = <0x2>;
232 - next-level-cache = <&L2_0>;
233 + next-level-cache = <&l2_0>;
234 };
235
236 - CPU3: cpu@3 {
237 + cpu3: cpu@3 {
238 device_type = "cpu";
239 compatible = "arm,cortex-a53";
240 enable-method = "psci";
241 reg = <0x3>;
242 - next-level-cache = <&L2_0>;
243 + next-level-cache = <&l2_0>;
244 };
245
246 - L2_0: l2-cache {
247 + l2_0: l2-cache {
248 compatible = "cache";
249 cache-level = <2>;
250 cache-unified;
251 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
252 +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
253 @@ -33,12 +33,12 @@
254 #address-cells = <1>;
255 #size-cells = <0>;
256
257 - CPU0: cpu@0 {
258 + cpu0: cpu@0 {
259 device_type = "cpu";
260 compatible = "arm,cortex-a73";
261 reg = <0x0>;
262 enable-method = "psci";
263 - next-level-cache = <&L2_0>;
264 + next-level-cache = <&l2_0>;
265 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
266 clock-names = "cpu";
267 operating-points-v2 = <&cpu_opp_table>;
268 @@ -46,12 +46,12 @@
269 #cooling-cells = <2>;
270 };
271
272 - CPU1: cpu@1 {
273 + cpu1: cpu@1 {
274 device_type = "cpu";
275 compatible = "arm,cortex-a73";
276 reg = <0x1>;
277 enable-method = "psci";
278 - next-level-cache = <&L2_0>;
279 + next-level-cache = <&l2_0>;
280 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
281 clock-names = "cpu";
282 operating-points-v2 = <&cpu_opp_table>;
283 @@ -59,12 +59,12 @@
284 #cooling-cells = <2>;
285 };
286
287 - CPU2: cpu@2 {
288 + cpu2: cpu@2 {
289 device_type = "cpu";
290 compatible = "arm,cortex-a73";
291 reg = <0x2>;
292 enable-method = "psci";
293 - next-level-cache = <&L2_0>;
294 + next-level-cache = <&l2_0>;
295 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
296 clock-names = "cpu";
297 operating-points-v2 = <&cpu_opp_table>;
298 @@ -72,12 +72,12 @@
299 #cooling-cells = <2>;
300 };
301
302 - CPU3: cpu@3 {
303 + cpu3: cpu@3 {
304 device_type = "cpu";
305 compatible = "arm,cortex-a73";
306 reg = <0x3>;
307 enable-method = "psci";
308 - next-level-cache = <&L2_0>;
309 + next-level-cache = <&l2_0>;
310 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
311 clock-names = "cpu";
312 operating-points-v2 = <&cpu_opp_table>;
313 @@ -85,7 +85,7 @@
314 #cooling-cells = <2>;
315 };
316
317 - L2_0: l2-cache {
318 + l2_0: l2-cache {
319 compatible = "cache";
320 cache-level = <2>;
321 cache-unified;
322 @@ -845,10 +845,10 @@
323 cooling-maps {
324 map0 {
325 trip = <&cpu0_alert>;
326 - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
327 - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
328 - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
329 - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
330 + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
331 + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
332 + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
333 + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
334 };
335 };
336 };
337 @@ -875,10 +875,10 @@
338 cooling-maps {
339 map0 {
340 trip = <&cpu1_alert>;
341 - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
342 - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
343 - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
344 - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
345 + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
346 + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
347 + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
348 + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
349 };
350 };
351 };
352 @@ -905,10 +905,10 @@
353 cooling-maps {
354 map0 {
355 trip = <&cpu2_alert>;
356 - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
357 - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
358 - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
359 - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
360 + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
361 + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
362 + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
363 + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
364 };
365 };
366 };
367 @@ -935,10 +935,10 @@
368 cooling-maps {
369 map0 {
370 trip = <&cpu3_alert>;
371 - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
372 - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
373 - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
374 - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
375 + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
376 + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
377 + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
378 + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
379 };
380 };
381 };
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