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1 From 86db870d9e00b71fb3bd2c8a1a72cda971d9a77d Mon Sep 17 00:00:00 2001
2 From: Devi Priya <quic_devipriy@quicinc.com>
3 Date: Fri, 25 Oct 2024 09:25:18 +0530
4 Subject: [PATCH 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
5
6 Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574 based
7 devices.
8
9 Reported-by: kernel test robot <lkp@intel.com>
10 Closes: https://lore.kernel.org/oe-kbuild-all/202410101431.tjpSRNTY-lkp@intel.com/
11 Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
12 Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
13 ---
14 drivers/clk/qcom/Kconfig | 7 +
15 drivers/clk/qcom/Makefile | 1 +
16 drivers/clk/qcom/nsscc-ipq9574.c | 3080 ++++++++++++++++++++++++++++++
17 3 files changed, 3088 insertions(+)
18 create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
19
20 --- a/drivers/clk/qcom/Kconfig
21 +++ b/drivers/clk/qcom/Kconfig
22 @@ -215,6 +215,13 @@ config IPQ_GCC_9574
23 i2c, USB, SD/eMMC, etc. Select this for the root clock
24 of ipq9574.
25
26 +config IPQ_NSSCC_9574
27 + tristate "IPQ9574 NSS Clock Controller"
28 + depends on ARM64 || COMPILE_TEST
29 + depends on IPQ_GCC_9574
30 + help
31 + Support for NSS clock controller on ipq9574 devices.
32 +
33 config IPQ_NSSCC_QCA8K
34 tristate "QCA8K(QCA8386 or QCA8084) NSS Clock Controller"
35 depends on MDIO_BUS || COMPILE_TEST
36 --- a/drivers/clk/qcom/Makefile
37 +++ b/drivers/clk/qcom/Makefile
38 @@ -31,6 +31,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq601
39 obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
40 obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
41 obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
42 +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
43 obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
44 obj-$(CONFIG_IPQ_NSSCC_QCA8K) += nsscc-qca8k.o
45 obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
46 --- /dev/null
47 +++ b/drivers/clk/qcom/nsscc-ipq9574.c
48 @@ -0,0 +1,3080 @@
49 +// SPDX-License-Identifier: GPL-2.0-only
50 +/*
51 + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
52 + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
53 + */
54 +
55 +#include <linux/clk.h>
56 +#include <linux/clk-provider.h>
57 +#include <linux/err.h>
58 +#include <linux/interconnect-provider.h>
59 +#include <linux/kernel.h>
60 +#include <linux/module.h>
61 +#include <linux/of.h>
62 +#include <linux/of_device.h>
63 +#include <linux/regmap.h>
64 +#include <linux/platform_device.h>
65 +
66 +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
67 +#include <dt-bindings/interconnect/qcom,ipq9574.h>
68 +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
69 +
70 +#include "clk-alpha-pll.h"
71 +#include "clk-branch.h"
72 +#include "clk-pll.h"
73 +#include "clk-rcg.h"
74 +#include "clk-regmap.h"
75 +#include "clk-regmap-divider.h"
76 +#include "clk-regmap-mux.h"
77 +#include "common.h"
78 +#include "reset.h"
79 +
80 +/* Need to match the order of clocks in DT binding */
81 +enum {
82 + DT_XO,
83 + DT_BIAS_PLL_CC_CLK,
84 + DT_BIAS_PLL_UBI_NC_CLK,
85 + DT_GCC_GPLL0_OUT_AUX,
86 + DT_UNIPHY0_NSS_RX_CLK,
87 + DT_UNIPHY0_NSS_TX_CLK,
88 + DT_UNIPHY1_NSS_RX_CLK,
89 + DT_UNIPHY1_NSS_TX_CLK,
90 + DT_UNIPHY2_NSS_RX_CLK,
91 + DT_UNIPHY2_NSS_TX_CLK,
92 +};
93 +
94 +enum {
95 + P_XO,
96 + P_BIAS_PLL_CC_CLK,
97 + P_BIAS_PLL_UBI_NC_CLK,
98 + P_GCC_GPLL0_OUT_AUX,
99 + P_UBI32_PLL_OUT_MAIN,
100 + P_UNIPHY0_NSS_RX_CLK,
101 + P_UNIPHY0_NSS_TX_CLK,
102 + P_UNIPHY1_NSS_RX_CLK,
103 + P_UNIPHY1_NSS_TX_CLK,
104 + P_UNIPHY2_NSS_RX_CLK,
105 + P_UNIPHY2_NSS_TX_CLK,
106 +};
107 +
108 +static const struct alpha_pll_config ubi32_pll_config = {
109 + .l = 0x3e,
110 + .alpha = 0x6666,
111 + .config_ctl_val = 0x200d4aa8,
112 + .config_ctl_hi_val = 0x3c,
113 + .main_output_mask = BIT(0),
114 + .aux_output_mask = BIT(1),
115 + .pre_div_val = 0x0,
116 + .pre_div_mask = BIT(12),
117 + .post_div_val = 0x0,
118 + .post_div_mask = GENMASK(9, 8),
119 + .alpha_en_mask = BIT(24),
120 + .test_ctl_val = 0x1c0000c0,
121 + .test_ctl_hi_val = 0x4000,
122 +};
123 +
124 +static struct clk_alpha_pll ubi32_pll_main = {
125 + .offset = 0x28000,
126 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
127 + .flags = SUPPORTS_DYNAMIC_UPDATE,
128 + .clkr = {
129 + .hw.init = &(const struct clk_init_data) {
130 + .name = "ubi32_pll_main",
131 + .parent_data = &(const struct clk_parent_data) {
132 + .index = DT_XO,
133 + },
134 + .num_parents = 1,
135 + .ops = &clk_alpha_pll_huayra_ops,
136 + },
137 + },
138 +};
139 +
140 +static struct clk_alpha_pll_postdiv ubi32_pll = {
141 + .offset = 0x28000,
142 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
143 + .width = 2,
144 + .clkr.hw.init = &(const struct clk_init_data) {
145 + .name = "ubi32_pll",
146 + .parent_hws = (const struct clk_hw *[]) {
147 + &ubi32_pll_main.clkr.hw
148 + },
149 + .num_parents = 1,
150 + .ops = &clk_alpha_pll_postdiv_ro_ops,
151 + .flags = CLK_SET_RATE_PARENT,
152 + },
153 +};
154 +
155 +static const struct parent_map nss_cc_parent_map_0[] = {
156 + { P_XO, 0 },
157 + { P_BIAS_PLL_CC_CLK, 1 },
158 + { P_UNIPHY0_NSS_RX_CLK, 2 },
159 + { P_UNIPHY0_NSS_TX_CLK, 3 },
160 + { P_UNIPHY1_NSS_RX_CLK, 4 },
161 + { P_UNIPHY1_NSS_TX_CLK, 5 },
162 +};
163 +
164 +static const struct clk_parent_data nss_cc_parent_data_0[] = {
165 + { .index = DT_XO },
166 + { .index = DT_BIAS_PLL_CC_CLK },
167 + { .index = DT_UNIPHY0_NSS_RX_CLK },
168 + { .index = DT_UNIPHY0_NSS_TX_CLK },
169 + { .index = DT_UNIPHY1_NSS_RX_CLK },
170 + { .index = DT_UNIPHY1_NSS_TX_CLK },
171 +};
172 +
173 +static const struct parent_map nss_cc_parent_map_1[] = {
174 + { P_XO, 0 },
175 + { P_BIAS_PLL_UBI_NC_CLK, 1 },
176 + { P_GCC_GPLL0_OUT_AUX, 2 },
177 + { P_BIAS_PLL_CC_CLK, 6 },
178 +};
179 +
180 +static const struct clk_parent_data nss_cc_parent_data_1[] = {
181 + { .index = DT_XO },
182 + { .index = DT_BIAS_PLL_UBI_NC_CLK },
183 + { .index = DT_GCC_GPLL0_OUT_AUX },
184 + { .index = DT_BIAS_PLL_CC_CLK },
185 +};
186 +
187 +static const struct parent_map nss_cc_parent_map_2[] = {
188 + { P_XO, 0 },
189 + { P_UBI32_PLL_OUT_MAIN, 1 },
190 + { P_GCC_GPLL0_OUT_AUX, 2 },
191 +};
192 +
193 +static const struct clk_parent_data nss_cc_parent_data_2[] = {
194 + { .index = DT_XO },
195 + { .hw = &ubi32_pll.clkr.hw },
196 + { .index = DT_GCC_GPLL0_OUT_AUX },
197 +};
198 +
199 +static const struct parent_map nss_cc_parent_map_3[] = {
200 + { P_XO, 0 },
201 + { P_BIAS_PLL_CC_CLK, 1 },
202 + { P_GCC_GPLL0_OUT_AUX, 2 },
203 +};
204 +
205 +static const struct clk_parent_data nss_cc_parent_data_3[] = {
206 + { .index = DT_XO },
207 + { .index = DT_BIAS_PLL_CC_CLK },
208 + { .index = DT_GCC_GPLL0_OUT_AUX },
209 +};
210 +
211 +static const struct parent_map nss_cc_parent_map_4[] = {
212 + { P_XO, 0 },
213 + { P_BIAS_PLL_CC_CLK, 1 },
214 + { P_UNIPHY0_NSS_RX_CLK, 2 },
215 + { P_UNIPHY0_NSS_TX_CLK, 3 },
216 +};
217 +
218 +static const struct clk_parent_data nss_cc_parent_data_4[] = {
219 + { .index = DT_XO },
220 + { .index = DT_BIAS_PLL_CC_CLK },
221 + { .index = DT_UNIPHY0_NSS_RX_CLK },
222 + { .index = DT_UNIPHY0_NSS_TX_CLK },
223 +};
224 +
225 +static const struct parent_map nss_cc_parent_map_5[] = {
226 + { P_XO, 0 },
227 + { P_BIAS_PLL_CC_CLK, 1 },
228 + { P_UNIPHY2_NSS_RX_CLK, 2 },
229 + { P_UNIPHY2_NSS_TX_CLK, 3 },
230 +};
231 +
232 +static const struct clk_parent_data nss_cc_parent_data_5[] = {
233 + { .index = DT_XO },
234 + { .index = DT_BIAS_PLL_CC_CLK },
235 + { .index = DT_UNIPHY2_NSS_RX_CLK },
236 + { .index = DT_UNIPHY2_NSS_TX_CLK },
237 +};
238 +
239 +static const struct parent_map nss_cc_parent_map_6[] = {
240 + { P_XO, 0 },
241 + { P_GCC_GPLL0_OUT_AUX, 2 },
242 + { P_BIAS_PLL_CC_CLK, 6 },
243 +};
244 +
245 +static const struct clk_parent_data nss_cc_parent_data_6[] = {
246 + { .index = DT_XO },
247 + { .index = DT_GCC_GPLL0_OUT_AUX },
248 + { .index = DT_BIAS_PLL_CC_CLK },
249 +};
250 +
251 +static const struct parent_map nss_cc_parent_map_7[] = {
252 + { P_XO, 0 },
253 + { P_UBI32_PLL_OUT_MAIN, 1 },
254 + { P_GCC_GPLL0_OUT_AUX, 2 },
255 + { P_BIAS_PLL_CC_CLK, 6 },
256 +};
257 +
258 +static const struct clk_parent_data nss_cc_parent_data_7[] = {
259 + { .index = DT_XO },
260 + { .hw = &ubi32_pll.clkr.hw },
261 + { .index = DT_GCC_GPLL0_OUT_AUX },
262 + { .index = DT_BIAS_PLL_CC_CLK },
263 +};
264 +
265 +static const struct freq_tbl ftbl_nss_cc_ce_clk_src[] = {
266 + F(24000000, P_XO, 1, 0, 0),
267 + F(353000000, P_BIAS_PLL_UBI_NC_CLK, 1, 0, 0),
268 + { }
269 +};
270 +
271 +static struct clk_rcg2 nss_cc_ce_clk_src = {
272 + .cmd_rcgr = 0x28404,
273 + .mnd_width = 0,
274 + .hid_width = 5,
275 + .parent_map = nss_cc_parent_map_1,
276 + .freq_tbl = ftbl_nss_cc_ce_clk_src,
277 + .clkr.hw.init = &(const struct clk_init_data) {
278 + .name = "nss_cc_ce_clk_src",
279 + .parent_data = nss_cc_parent_data_1,
280 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
281 + .ops = &clk_rcg2_ops,
282 + },
283 +};
284 +
285 +static const struct freq_tbl ftbl_nss_cc_cfg_clk_src[] = {
286 + F(100000000, P_GCC_GPLL0_OUT_AUX, 8, 0, 0),
287 + { }
288 +};
289 +
290 +static struct clk_rcg2 nss_cc_cfg_clk_src = {
291 + .cmd_rcgr = 0x28104,
292 + .mnd_width = 0,
293 + .hid_width = 5,
294 + .parent_map = nss_cc_parent_map_3,
295 + .freq_tbl = ftbl_nss_cc_cfg_clk_src,
296 + .clkr.hw.init = &(const struct clk_init_data) {
297 + .name = "nss_cc_cfg_clk_src",
298 + .parent_data = nss_cc_parent_data_3,
299 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
300 + .ops = &clk_rcg2_ops,
301 + },
302 +};
303 +
304 +static const struct freq_tbl ftbl_nss_cc_clc_clk_src[] = {
305 + F(533333333, P_GCC_GPLL0_OUT_AUX, 1.5, 0, 0),
306 + { }
307 +};
308 +
309 +static struct clk_rcg2 nss_cc_clc_clk_src = {
310 + .cmd_rcgr = 0x28604,
311 + .mnd_width = 0,
312 + .hid_width = 5,
313 + .parent_map = nss_cc_parent_map_6,
314 + .freq_tbl = ftbl_nss_cc_clc_clk_src,
315 + .clkr.hw.init = &(const struct clk_init_data) {
316 + .name = "nss_cc_clc_clk_src",
317 + .parent_data = nss_cc_parent_data_6,
318 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_6),
319 + .ops = &clk_rcg2_ops,
320 + },
321 +};
322 +
323 +static const struct freq_tbl ftbl_nss_cc_crypto_clk_src[] = {
324 + F(24000000, P_XO, 1, 0, 0),
325 + F(300000000, P_BIAS_PLL_CC_CLK, 4, 0, 0),
326 + F(600000000, P_BIAS_PLL_CC_CLK, 2, 0, 0),
327 + { }
328 +};
329 +
330 +static struct clk_rcg2 nss_cc_crypto_clk_src = {
331 + .cmd_rcgr = 0x16008,
332 + .mnd_width = 16,
333 + .hid_width = 5,
334 + .parent_map = nss_cc_parent_map_3,
335 + .freq_tbl = ftbl_nss_cc_crypto_clk_src,
336 + .clkr.hw.init = &(const struct clk_init_data) {
337 + .name = "nss_cc_crypto_clk_src",
338 + .parent_data = nss_cc_parent_data_3,
339 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
340 + .flags = CLK_SET_RATE_PARENT,
341 + .ops = &clk_rcg2_ops,
342 + },
343 +};
344 +
345 +static struct clk_rcg2 nss_cc_haq_clk_src = {
346 + .cmd_rcgr = 0x28304,
347 + .mnd_width = 0,
348 + .hid_width = 5,
349 + .parent_map = nss_cc_parent_map_1,
350 + .freq_tbl = ftbl_nss_cc_ce_clk_src,
351 + .clkr.hw.init = &(const struct clk_init_data) {
352 + .name = "nss_cc_haq_clk_src",
353 + .parent_data = nss_cc_parent_data_1,
354 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
355 + .ops = &clk_rcg2_ops,
356 + },
357 +};
358 +
359 +static struct clk_rcg2 nss_cc_imem_clk_src = {
360 + .cmd_rcgr = 0xe008,
361 + .mnd_width = 0,
362 + .hid_width = 5,
363 + .parent_map = nss_cc_parent_map_1,
364 + .freq_tbl = ftbl_nss_cc_ce_clk_src,
365 + .clkr.hw.init = &(const struct clk_init_data) {
366 + .name = "nss_cc_imem_clk_src",
367 + .parent_data = nss_cc_parent_data_1,
368 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
369 + .ops = &clk_rcg2_ops,
370 + },
371 +};
372 +
373 +static const struct freq_tbl ftbl_nss_cc_int_cfg_clk_src[] = {
374 + F(200000000, P_GCC_GPLL0_OUT_AUX, 4, 0, 0),
375 + { }
376 +};
377 +
378 +static struct clk_rcg2 nss_cc_int_cfg_clk_src = {
379 + .cmd_rcgr = 0x287b4,
380 + .mnd_width = 0,
381 + .hid_width = 5,
382 + .parent_map = nss_cc_parent_map_3,
383 + .freq_tbl = ftbl_nss_cc_int_cfg_clk_src,
384 + .clkr.hw.init = &(const struct clk_init_data) {
385 + .name = "nss_cc_int_cfg_clk_src",
386 + .parent_data = nss_cc_parent_data_3,
387 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
388 + .ops = &clk_rcg2_ops,
389 + },
390 +};
391 +
392 +static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
393 + C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0),
394 + C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
395 +};
396 +
397 +static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] = {
398 + C(P_UNIPHY0_NSS_RX_CLK, 2.5, 0, 0),
399 + C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
400 +};
401 +
402 +static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
403 + FMS(24000000, P_XO, 1, 0, 0),
404 + FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25),
405 + FMS(78125000, P_UNIPHY0_NSS_RX_CLK, 4, 0, 0),
406 + FM(125000000, ftbl_nss_cc_port1_rx_clk_src_125),
407 + FMS(312500000, P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
408 + { }
409 +};
410 +
411 +static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_25[] = {
412 + C(P_UNIPHY0_NSS_TX_CLK, 12.5, 0, 0),
413 + C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0),
414 +};
415 +
416 +static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_125[] = {
417 + C(P_UNIPHY0_NSS_TX_CLK, 2.5, 0, 0),
418 + C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
419 +};
420 +
421 +static const struct freq_multi_tbl ftbl_nss_cc_port1_tx_clk_src[] = {
422 + FMS(24000000, P_XO, 1, 0, 0),
423 + FM(25000000, ftbl_nss_cc_port1_tx_clk_src_25),
424 + FMS(78125000, P_UNIPHY0_NSS_TX_CLK, 4, 0, 0),
425 + FM(125000000, ftbl_nss_cc_port1_tx_clk_src_125),
426 + FMS(312500000, P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
427 + { }
428 +};
429 +
430 +static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_25[] = {
431 + C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0),
432 + C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
433 +};
434 +
435 +static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_125[] = {
436 + C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0),
437 + C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
438 +};
439 +
440 +static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_312p5[] = {
441 + C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0),
442 + C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
443 +};
444 +
445 +static const struct freq_multi_tbl ftbl_nss_cc_port5_rx_clk_src[] = {
446 + FMS(24000000, P_XO, 1, 0, 0),
447 + FM(25000000, ftbl_nss_cc_port5_rx_clk_src_25),
448 + FMS(78125000, P_UNIPHY1_NSS_RX_CLK, 4, 0, 0),
449 + FM(125000000, ftbl_nss_cc_port5_rx_clk_src_125),
450 + FMS(156250000, P_UNIPHY1_NSS_RX_CLK, 2, 0, 0),
451 + FM(312500000, ftbl_nss_cc_port5_rx_clk_src_312p5),
452 + { }
453 +};
454 +
455 +static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_25[] = {
456 + C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0),
457 + C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0),
458 +};
459 +
460 +static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_125[] = {
461 + C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0),
462 + C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
463 +};
464 +
465 +static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_312p5[] = {
466 + C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0),
467 + C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
468 +};
469 +
470 +static const struct freq_multi_tbl ftbl_nss_cc_port5_tx_clk_src[] = {
471 + FMS(24000000, P_XO, 1, 0, 0),
472 + FM(25000000, ftbl_nss_cc_port5_tx_clk_src_25),
473 + FMS(78125000, P_UNIPHY1_NSS_TX_CLK, 4, 0, 0),
474 + FM(125000000, ftbl_nss_cc_port5_tx_clk_src_125),
475 + FMS(156250000, P_UNIPHY1_NSS_TX_CLK, 2, 0, 0),
476 + FM(312500000, ftbl_nss_cc_port5_tx_clk_src_312p5),
477 + { }
478 +};
479 +
480 +static const struct freq_conf ftbl_nss_cc_port6_rx_clk_src_25[] = {
481 + C(P_UNIPHY2_NSS_RX_CLK, 12.5, 0, 0),
482 + C(P_UNIPHY2_NSS_RX_CLK, 5, 0, 0),
483 +};
484 +
485 +static const struct freq_conf ftbl_nss_cc_port6_rx_clk_src_125[] = {
486 + C(P_UNIPHY2_NSS_RX_CLK, 2.5, 0, 0),
487 + C(P_UNIPHY2_NSS_RX_CLK, 1, 0, 0),
488 +};
489 +
490 +static const struct freq_multi_tbl ftbl_nss_cc_port6_rx_clk_src[] = {
491 + FMS(24000000, P_XO, 1, 0, 0),
492 + FM(25000000, ftbl_nss_cc_port6_rx_clk_src_25),
493 + FMS(78125000, P_UNIPHY2_NSS_RX_CLK, 4, 0, 0),
494 + FM(125000000, ftbl_nss_cc_port6_rx_clk_src_125),
495 + FMS(156250000, P_UNIPHY2_NSS_RX_CLK, 2, 0, 0),
496 + FMS(312500000, P_UNIPHY2_NSS_RX_CLK, 1, 0, 0),
497 + { }
498 +};
499 +
500 +static const struct freq_conf ftbl_nss_cc_port6_tx_clk_src_25[] = {
501 + C(P_UNIPHY2_NSS_TX_CLK, 12.5, 0, 0),
502 + C(P_UNIPHY2_NSS_TX_CLK, 5, 0, 0),
503 +};
504 +
505 +static const struct freq_conf ftbl_nss_cc_port6_tx_clk_src_125[] = {
506 + C(P_UNIPHY2_NSS_TX_CLK, 2.5, 0, 0),
507 + C(P_UNIPHY2_NSS_TX_CLK, 1, 0, 0),
508 +};
509 +
510 +static const struct freq_multi_tbl ftbl_nss_cc_port6_tx_clk_src[] = {
511 + FMS(24000000, P_XO, 1, 0, 0),
512 + FM(25000000, ftbl_nss_cc_port6_tx_clk_src_25),
513 + FMS(78125000, P_UNIPHY2_NSS_TX_CLK, 4, 0, 0),
514 + FM(125000000, ftbl_nss_cc_port6_tx_clk_src_125),
515 + FMS(156250000, P_UNIPHY2_NSS_TX_CLK, 2, 0, 0),
516 + FMS(312500000, P_UNIPHY2_NSS_TX_CLK, 1, 0, 0),
517 + { }
518 +};
519 +
520 +static struct clk_rcg2 nss_cc_port1_rx_clk_src = {
521 + .cmd_rcgr = 0x28110,
522 + .mnd_width = 0,
523 + .hid_width = 5,
524 + .parent_map = nss_cc_parent_map_4,
525 + .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
526 + .clkr.hw.init = &(const struct clk_init_data) {
527 + .name = "nss_cc_port1_rx_clk_src",
528 + .parent_data = nss_cc_parent_data_4,
529 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
530 + .ops = &clk_rcg2_fm_ops,
531 + },
532 +};
533 +
534 +static struct clk_rcg2 nss_cc_port1_tx_clk_src = {
535 + .cmd_rcgr = 0x2811c,
536 + .mnd_width = 0,
537 + .hid_width = 5,
538 + .parent_map = nss_cc_parent_map_4,
539 + .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
540 + .clkr.hw.init = &(const struct clk_init_data) {
541 + .name = "nss_cc_port1_tx_clk_src",
542 + .parent_data = nss_cc_parent_data_4,
543 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
544 + .ops = &clk_rcg2_fm_ops,
545 + },
546 +};
547 +
548 +static struct clk_rcg2 nss_cc_port2_rx_clk_src = {
549 + .cmd_rcgr = 0x28128,
550 + .mnd_width = 0,
551 + .hid_width = 5,
552 + .parent_map = nss_cc_parent_map_4,
553 + .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
554 + .clkr.hw.init = &(const struct clk_init_data) {
555 + .name = "nss_cc_port2_rx_clk_src",
556 + .parent_data = nss_cc_parent_data_4,
557 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
558 + .ops = &clk_rcg2_fm_ops,
559 + },
560 +};
561 +
562 +static struct clk_rcg2 nss_cc_port2_tx_clk_src = {
563 + .cmd_rcgr = 0x28134,
564 + .mnd_width = 0,
565 + .hid_width = 5,
566 + .parent_map = nss_cc_parent_map_4,
567 + .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
568 + .clkr.hw.init = &(const struct clk_init_data) {
569 + .name = "nss_cc_port2_tx_clk_src",
570 + .parent_data = nss_cc_parent_data_4,
571 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
572 + .ops = &clk_rcg2_fm_ops,
573 + },
574 +};
575 +
576 +static struct clk_rcg2 nss_cc_port3_rx_clk_src = {
577 + .cmd_rcgr = 0x28140,
578 + .mnd_width = 0,
579 + .hid_width = 5,
580 + .parent_map = nss_cc_parent_map_4,
581 + .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
582 + .clkr.hw.init = &(const struct clk_init_data) {
583 + .name = "nss_cc_port3_rx_clk_src",
584 + .parent_data = nss_cc_parent_data_4,
585 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
586 + .ops = &clk_rcg2_fm_ops,
587 + },
588 +};
589 +
590 +static struct clk_rcg2 nss_cc_port3_tx_clk_src = {
591 + .cmd_rcgr = 0x2814c,
592 + .mnd_width = 0,
593 + .hid_width = 5,
594 + .parent_map = nss_cc_parent_map_4,
595 + .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
596 + .clkr.hw.init = &(const struct clk_init_data) {
597 + .name = "nss_cc_port3_tx_clk_src",
598 + .parent_data = nss_cc_parent_data_4,
599 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
600 + .ops = &clk_rcg2_fm_ops,
601 + },
602 +};
603 +
604 +static struct clk_rcg2 nss_cc_port4_rx_clk_src = {
605 + .cmd_rcgr = 0x28158,
606 + .mnd_width = 0,
607 + .hid_width = 5,
608 + .parent_map = nss_cc_parent_map_4,
609 + .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
610 + .clkr.hw.init = &(const struct clk_init_data) {
611 + .name = "nss_cc_port4_rx_clk_src",
612 + .parent_data = nss_cc_parent_data_4,
613 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
614 + .ops = &clk_rcg2_fm_ops,
615 + },
616 +};
617 +
618 +static struct clk_rcg2 nss_cc_port4_tx_clk_src = {
619 + .cmd_rcgr = 0x28164,
620 + .mnd_width = 0,
621 + .hid_width = 5,
622 + .parent_map = nss_cc_parent_map_4,
623 + .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
624 + .clkr.hw.init = &(const struct clk_init_data) {
625 + .name = "nss_cc_port4_tx_clk_src",
626 + .parent_data = nss_cc_parent_data_4,
627 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
628 + .ops = &clk_rcg2_fm_ops,
629 + },
630 +};
631 +
632 +static struct clk_rcg2 nss_cc_port5_rx_clk_src = {
633 + .cmd_rcgr = 0x28170,
634 + .mnd_width = 0,
635 + .hid_width = 5,
636 + .parent_map = nss_cc_parent_map_0,
637 + .freq_multi_tbl = ftbl_nss_cc_port5_rx_clk_src,
638 + .clkr.hw.init = &(const struct clk_init_data) {
639 + .name = "nss_cc_port5_rx_clk_src",
640 + .parent_data = nss_cc_parent_data_0,
641 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
642 + .ops = &clk_rcg2_fm_ops,
643 + },
644 +};
645 +
646 +static struct clk_rcg2 nss_cc_port5_tx_clk_src = {
647 + .cmd_rcgr = 0x2817c,
648 + .mnd_width = 0,
649 + .hid_width = 5,
650 + .parent_map = nss_cc_parent_map_0,
651 + .freq_multi_tbl = ftbl_nss_cc_port5_tx_clk_src,
652 + .clkr.hw.init = &(const struct clk_init_data) {
653 + .name = "nss_cc_port5_tx_clk_src",
654 + .parent_data = nss_cc_parent_data_0,
655 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
656 + .ops = &clk_rcg2_fm_ops,
657 + },
658 +};
659 +
660 +static struct clk_rcg2 nss_cc_port6_rx_clk_src = {
661 + .cmd_rcgr = 0x28188,
662 + .mnd_width = 0,
663 + .hid_width = 5,
664 + .parent_map = nss_cc_parent_map_5,
665 + .freq_multi_tbl = ftbl_nss_cc_port6_rx_clk_src,
666 + .clkr.hw.init = &(const struct clk_init_data) {
667 + .name = "nss_cc_port6_rx_clk_src",
668 + .parent_data = nss_cc_parent_data_5,
669 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_5),
670 + .ops = &clk_rcg2_fm_ops,
671 + },
672 +};
673 +
674 +static struct clk_rcg2 nss_cc_port6_tx_clk_src = {
675 + .cmd_rcgr = 0x28194,
676 + .mnd_width = 0,
677 + .hid_width = 5,
678 + .parent_map = nss_cc_parent_map_5,
679 + .freq_multi_tbl = ftbl_nss_cc_port6_tx_clk_src,
680 + .clkr.hw.init = &(const struct clk_init_data) {
681 + .name = "nss_cc_port6_tx_clk_src",
682 + .parent_data = nss_cc_parent_data_5,
683 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_5),
684 + .ops = &clk_rcg2_fm_ops,
685 + },
686 +};
687 +
688 +static struct clk_rcg2 nss_cc_ppe_clk_src = {
689 + .cmd_rcgr = 0x28204,
690 + .mnd_width = 0,
691 + .hid_width = 5,
692 + .parent_map = nss_cc_parent_map_1,
693 + .freq_tbl = ftbl_nss_cc_ce_clk_src,
694 + .clkr.hw.init = &(const struct clk_init_data) {
695 + .name = "nss_cc_ppe_clk_src",
696 + .parent_data = nss_cc_parent_data_1,
697 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
698 + .flags = CLK_SET_RATE_PARENT,
699 + .ops = &clk_rcg2_ops,
700 + },
701 +};
702 +
703 +static const struct freq_tbl ftbl_nss_cc_ubi0_clk_src[] = {
704 + F(24000000, P_XO, 1, 0, 0),
705 + F(187200000, P_UBI32_PLL_OUT_MAIN, 8, 0, 0),
706 + F(748800000, P_UBI32_PLL_OUT_MAIN, 2, 0, 0),
707 + F(1497600000, P_UBI32_PLL_OUT_MAIN, 1, 0, 0),
708 + F(1689600000, P_UBI32_PLL_OUT_MAIN, 1, 0, 0),
709 + { }
710 +};
711 +
712 +static struct clk_rcg2 nss_cc_ubi0_clk_src = {
713 + .cmd_rcgr = 0x28704,
714 + .mnd_width = 0,
715 + .hid_width = 5,
716 + .parent_map = nss_cc_parent_map_2,
717 + .freq_tbl = ftbl_nss_cc_ubi0_clk_src,
718 + .clkr.hw.init = &(const struct clk_init_data) {
719 + .name = "nss_cc_ubi0_clk_src",
720 + .parent_data = nss_cc_parent_data_2,
721 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
722 + .flags = CLK_SET_RATE_PARENT,
723 + .ops = &clk_rcg2_ops,
724 + },
725 +};
726 +
727 +static struct clk_rcg2 nss_cc_ubi1_clk_src = {
728 + .cmd_rcgr = 0x2870c,
729 + .mnd_width = 0,
730 + .hid_width = 5,
731 + .parent_map = nss_cc_parent_map_2,
732 + .freq_tbl = ftbl_nss_cc_ubi0_clk_src,
733 + .clkr.hw.init = &(const struct clk_init_data) {
734 + .name = "nss_cc_ubi1_clk_src",
735 + .parent_data = nss_cc_parent_data_2,
736 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
737 + .flags = CLK_SET_RATE_PARENT,
738 + .ops = &clk_rcg2_ops,
739 + },
740 +};
741 +
742 +static struct clk_rcg2 nss_cc_ubi2_clk_src = {
743 + .cmd_rcgr = 0x28714,
744 + .mnd_width = 0,
745 + .hid_width = 5,
746 + .parent_map = nss_cc_parent_map_2,
747 + .freq_tbl = ftbl_nss_cc_ubi0_clk_src,
748 + .clkr.hw.init = &(const struct clk_init_data) {
749 + .name = "nss_cc_ubi2_clk_src",
750 + .parent_data = nss_cc_parent_data_2,
751 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
752 + .flags = CLK_SET_RATE_PARENT,
753 + .ops = &clk_rcg2_ops,
754 + },
755 +};
756 +
757 +static struct clk_rcg2 nss_cc_ubi3_clk_src = {
758 + .cmd_rcgr = 0x2871c,
759 + .mnd_width = 0,
760 + .hid_width = 5,
761 + .parent_map = nss_cc_parent_map_2,
762 + .freq_tbl = ftbl_nss_cc_ubi0_clk_src,
763 + .clkr.hw.init = &(const struct clk_init_data) {
764 + .name = "nss_cc_ubi3_clk_src",
765 + .parent_data = nss_cc_parent_data_2,
766 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
767 + .flags = CLK_SET_RATE_PARENT,
768 + .ops = &clk_rcg2_ops,
769 + },
770 +};
771 +
772 +static struct clk_rcg2 nss_cc_ubi_axi_clk_src = {
773 + .cmd_rcgr = 0x28724,
774 + .mnd_width = 0,
775 + .hid_width = 5,
776 + .parent_map = nss_cc_parent_map_7,
777 + .freq_tbl = ftbl_nss_cc_clc_clk_src,
778 + .clkr.hw.init = &(const struct clk_init_data) {
779 + .name = "nss_cc_ubi_axi_clk_src",
780 + .parent_data = nss_cc_parent_data_7,
781 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_7),
782 + .ops = &clk_rcg2_ops,
783 + },
784 +};
785 +
786 +static struct clk_rcg2 nss_cc_ubi_nc_axi_bfdcd_clk_src = {
787 + .cmd_rcgr = 0x2872c,
788 + .mnd_width = 0,
789 + .hid_width = 5,
790 + .parent_map = nss_cc_parent_map_1,
791 + .freq_tbl = ftbl_nss_cc_ce_clk_src,
792 + .clkr.hw.init = &(const struct clk_init_data) {
793 + .name = "nss_cc_ubi_nc_axi_bfdcd_clk_src",
794 + .parent_data = nss_cc_parent_data_1,
795 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
796 + .flags = CLK_SET_RATE_PARENT,
797 + .ops = &clk_rcg2_ops,
798 + },
799 +};
800 +
801 +static struct clk_regmap_div nss_cc_port1_rx_div_clk_src = {
802 + .reg = 0x28118,
803 + .shift = 0,
804 + .width = 9,
805 + .clkr.hw.init = &(const struct clk_init_data) {
806 + .name = "nss_cc_port1_rx_div_clk_src",
807 + .parent_data = &(const struct clk_parent_data) {
808 + .hw = &nss_cc_port1_rx_clk_src.clkr.hw,
809 + },
810 + .num_parents = 1,
811 + .flags = CLK_SET_RATE_PARENT,
812 + .ops = &clk_regmap_div_ops,
813 + },
814 +};
815 +
816 +static struct clk_regmap_div nss_cc_port1_tx_div_clk_src = {
817 + .reg = 0x28124,
818 + .shift = 0,
819 + .width = 9,
820 + .clkr.hw.init = &(const struct clk_init_data) {
821 + .name = "nss_cc_port1_tx_div_clk_src",
822 + .parent_data = &(const struct clk_parent_data) {
823 + .hw = &nss_cc_port1_tx_clk_src.clkr.hw,
824 + },
825 + .num_parents = 1,
826 + .flags = CLK_SET_RATE_PARENT,
827 + .ops = &clk_regmap_div_ops,
828 + },
829 +};
830 +
831 +static struct clk_regmap_div nss_cc_port2_rx_div_clk_src = {
832 + .reg = 0x28130,
833 + .shift = 0,
834 + .width = 9,
835 + .clkr.hw.init = &(const struct clk_init_data) {
836 + .name = "nss_cc_port2_rx_div_clk_src",
837 + .parent_data = &(const struct clk_parent_data) {
838 + .hw = &nss_cc_port2_rx_clk_src.clkr.hw,
839 + },
840 + .num_parents = 1,
841 + .flags = CLK_SET_RATE_PARENT,
842 + .ops = &clk_regmap_div_ops,
843 + },
844 +};
845 +
846 +static struct clk_regmap_div nss_cc_port2_tx_div_clk_src = {
847 + .reg = 0x2813c,
848 + .shift = 0,
849 + .width = 9,
850 + .clkr.hw.init = &(const struct clk_init_data) {
851 + .name = "nss_cc_port2_tx_div_clk_src",
852 + .parent_data = &(const struct clk_parent_data) {
853 + .hw = &nss_cc_port2_tx_clk_src.clkr.hw,
854 + },
855 + .num_parents = 1,
856 + .flags = CLK_SET_RATE_PARENT,
857 + .ops = &clk_regmap_div_ops,
858 + },
859 +};
860 +
861 +static struct clk_regmap_div nss_cc_port3_rx_div_clk_src = {
862 + .reg = 0x28148,
863 + .shift = 0,
864 + .width = 9,
865 + .clkr.hw.init = &(const struct clk_init_data) {
866 + .name = "nss_cc_port3_rx_div_clk_src",
867 + .parent_data = &(const struct clk_parent_data) {
868 + .hw = &nss_cc_port3_rx_clk_src.clkr.hw,
869 + },
870 + .num_parents = 1,
871 + .flags = CLK_SET_RATE_PARENT,
872 + .ops = &clk_regmap_div_ops,
873 + },
874 +};
875 +
876 +static struct clk_regmap_div nss_cc_port3_tx_div_clk_src = {
877 + .reg = 0x28154,
878 + .shift = 0,
879 + .width = 9,
880 + .clkr.hw.init = &(const struct clk_init_data) {
881 + .name = "nss_cc_port3_tx_div_clk_src",
882 + .parent_data = &(const struct clk_parent_data) {
883 + .hw = &nss_cc_port3_tx_clk_src.clkr.hw,
884 + },
885 + .num_parents = 1,
886 + .flags = CLK_SET_RATE_PARENT,
887 + .ops = &clk_regmap_div_ops,
888 + },
889 +};
890 +
891 +static struct clk_regmap_div nss_cc_port4_rx_div_clk_src = {
892 + .reg = 0x28160,
893 + .shift = 0,
894 + .width = 9,
895 + .clkr.hw.init = &(const struct clk_init_data) {
896 + .name = "nss_cc_port4_rx_div_clk_src",
897 + .parent_data = &(const struct clk_parent_data) {
898 + .hw = &nss_cc_port4_rx_clk_src.clkr.hw,
899 + },
900 + .num_parents = 1,
901 + .flags = CLK_SET_RATE_PARENT,
902 + .ops = &clk_regmap_div_ops,
903 + },
904 +};
905 +
906 +static struct clk_regmap_div nss_cc_port4_tx_div_clk_src = {
907 + .reg = 0x2816c,
908 + .shift = 0,
909 + .width = 9,
910 + .clkr.hw.init = &(const struct clk_init_data) {
911 + .name = "nss_cc_port4_tx_div_clk_src",
912 + .parent_data = &(const struct clk_parent_data) {
913 + .hw = &nss_cc_port4_tx_clk_src.clkr.hw,
914 + },
915 + .num_parents = 1,
916 + .flags = CLK_SET_RATE_PARENT,
917 + .ops = &clk_regmap_div_ops,
918 + },
919 +};
920 +
921 +static struct clk_regmap_div nss_cc_port5_rx_div_clk_src = {
922 + .reg = 0x28178,
923 + .shift = 0,
924 + .width = 9,
925 + .clkr.hw.init = &(const struct clk_init_data) {
926 + .name = "nss_cc_port5_rx_div_clk_src",
927 + .parent_data = &(const struct clk_parent_data) {
928 + .hw = &nss_cc_port5_rx_clk_src.clkr.hw,
929 + },
930 + .num_parents = 1,
931 + .flags = CLK_SET_RATE_PARENT,
932 + .ops = &clk_regmap_div_ops,
933 + },
934 +};
935 +
936 +static struct clk_regmap_div nss_cc_port5_tx_div_clk_src = {
937 + .reg = 0x28184,
938 + .shift = 0,
939 + .width = 9,
940 + .clkr.hw.init = &(const struct clk_init_data) {
941 + .name = "nss_cc_port5_tx_div_clk_src",
942 + .parent_data = &(const struct clk_parent_data) {
943 + .hw = &nss_cc_port5_tx_clk_src.clkr.hw,
944 + },
945 + .num_parents = 1,
946 + .flags = CLK_SET_RATE_PARENT,
947 + .ops = &clk_regmap_div_ops,
948 + },
949 +};
950 +
951 +static struct clk_regmap_div nss_cc_port6_rx_div_clk_src = {
952 + .reg = 0x28190,
953 + .shift = 0,
954 + .width = 9,
955 + .clkr.hw.init = &(const struct clk_init_data) {
956 + .name = "nss_cc_port6_rx_div_clk_src",
957 + .parent_data = &(const struct clk_parent_data) {
958 + .hw = &nss_cc_port6_rx_clk_src.clkr.hw,
959 + },
960 + .num_parents = 1,
961 + .flags = CLK_SET_RATE_PARENT,
962 + .ops = &clk_regmap_div_ops,
963 + },
964 +};
965 +
966 +static struct clk_regmap_div nss_cc_port6_tx_div_clk_src = {
967 + .reg = 0x2819c,
968 + .shift = 0,
969 + .width = 9,
970 + .clkr.hw.init = &(const struct clk_init_data) {
971 + .name = "nss_cc_port6_tx_div_clk_src",
972 + .parent_data = &(const struct clk_parent_data) {
973 + .hw = &nss_cc_port6_tx_clk_src.clkr.hw,
974 + },
975 + .num_parents = 1,
976 + .flags = CLK_SET_RATE_PARENT,
977 + .ops = &clk_regmap_div_ops,
978 + },
979 +};
980 +
981 +static struct clk_regmap_div nss_cc_ubi0_div_clk_src = {
982 + .reg = 0x287a4,
983 + .shift = 0,
984 + .width = 4,
985 + .clkr.hw.init = &(const struct clk_init_data) {
986 + .name = "nss_cc_ubi0_div_clk_src",
987 + .parent_data = &(const struct clk_parent_data) {
988 + .hw = &nss_cc_ubi0_clk_src.clkr.hw,
989 + },
990 + .num_parents = 1,
991 + .flags = CLK_SET_RATE_PARENT,
992 + .ops = &clk_regmap_div_ro_ops,
993 + },
994 +};
995 +
996 +static struct clk_regmap_div nss_cc_ubi1_div_clk_src = {
997 + .reg = 0x287a8,
998 + .shift = 0,
999 + .width = 4,
1000 + .clkr.hw.init = &(const struct clk_init_data) {
1001 + .name = "nss_cc_ubi1_div_clk_src",
1002 + .parent_data = &(const struct clk_parent_data) {
1003 + .hw = &nss_cc_ubi1_clk_src.clkr.hw,
1004 + },
1005 + .num_parents = 1,
1006 + .flags = CLK_SET_RATE_PARENT,
1007 + .ops = &clk_regmap_div_ro_ops,
1008 + },
1009 +};
1010 +
1011 +static struct clk_regmap_div nss_cc_ubi2_div_clk_src = {
1012 + .reg = 0x287ac,
1013 + .shift = 0,
1014 + .width = 4,
1015 + .clkr.hw.init = &(const struct clk_init_data) {
1016 + .name = "nss_cc_ubi2_div_clk_src",
1017 + .parent_data = &(const struct clk_parent_data) {
1018 + .hw = &nss_cc_ubi2_clk_src.clkr.hw,
1019 + },
1020 + .num_parents = 1,
1021 + .flags = CLK_SET_RATE_PARENT,
1022 + .ops = &clk_regmap_div_ro_ops,
1023 + },
1024 +};
1025 +
1026 +static struct clk_regmap_div nss_cc_ubi3_div_clk_src = {
1027 + .reg = 0x287b0,
1028 + .shift = 0,
1029 + .width = 4,
1030 + .clkr.hw.init = &(const struct clk_init_data) {
1031 + .name = "nss_cc_ubi3_div_clk_src",
1032 + .parent_data = &(const struct clk_parent_data) {
1033 + .hw = &nss_cc_ubi3_clk_src.clkr.hw,
1034 + },
1035 + .num_parents = 1,
1036 + .flags = CLK_SET_RATE_PARENT,
1037 + .ops = &clk_regmap_div_ro_ops,
1038 + },
1039 +};
1040 +
1041 +static struct clk_regmap_div nss_cc_xgmac0_ptp_ref_div_clk_src = {
1042 + .reg = 0x28214,
1043 + .shift = 0,
1044 + .width = 4,
1045 + .clkr.hw.init = &(const struct clk_init_data) {
1046 + .name = "nss_cc_xgmac0_ptp_ref_div_clk_src",
1047 + .parent_data = &(const struct clk_parent_data) {
1048 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1049 + },
1050 + .num_parents = 1,
1051 + .flags = CLK_SET_RATE_PARENT,
1052 + .ops = &clk_regmap_div_ro_ops,
1053 + },
1054 +};
1055 +
1056 +static struct clk_regmap_div nss_cc_xgmac1_ptp_ref_div_clk_src = {
1057 + .reg = 0x28218,
1058 + .shift = 0,
1059 + .width = 4,
1060 + .clkr.hw.init = &(const struct clk_init_data) {
1061 + .name = "nss_cc_xgmac1_ptp_ref_div_clk_src",
1062 + .parent_data = &(const struct clk_parent_data) {
1063 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1064 + },
1065 + .num_parents = 1,
1066 + .flags = CLK_SET_RATE_PARENT,
1067 + .ops = &clk_regmap_div_ro_ops,
1068 + },
1069 +};
1070 +
1071 +static struct clk_regmap_div nss_cc_xgmac2_ptp_ref_div_clk_src = {
1072 + .reg = 0x2821c,
1073 + .shift = 0,
1074 + .width = 4,
1075 + .clkr.hw.init = &(const struct clk_init_data) {
1076 + .name = "nss_cc_xgmac2_ptp_ref_div_clk_src",
1077 + .parent_data = &(const struct clk_parent_data) {
1078 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1079 + },
1080 + .num_parents = 1,
1081 + .flags = CLK_SET_RATE_PARENT,
1082 + .ops = &clk_regmap_div_ro_ops,
1083 + },
1084 +};
1085 +
1086 +static struct clk_regmap_div nss_cc_xgmac3_ptp_ref_div_clk_src = {
1087 + .reg = 0x28220,
1088 + .shift = 0,
1089 + .width = 4,
1090 + .clkr.hw.init = &(const struct clk_init_data) {
1091 + .name = "nss_cc_xgmac3_ptp_ref_div_clk_src",
1092 + .parent_data = &(const struct clk_parent_data) {
1093 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1094 + },
1095 + .num_parents = 1,
1096 + .flags = CLK_SET_RATE_PARENT,
1097 + .ops = &clk_regmap_div_ro_ops,
1098 + },
1099 +};
1100 +
1101 +static struct clk_regmap_div nss_cc_xgmac4_ptp_ref_div_clk_src = {
1102 + .reg = 0x28224,
1103 + .shift = 0,
1104 + .width = 4,
1105 + .clkr.hw.init = &(const struct clk_init_data) {
1106 + .name = "nss_cc_xgmac4_ptp_ref_div_clk_src",
1107 + .parent_data = &(const struct clk_parent_data) {
1108 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1109 + },
1110 + .num_parents = 1,
1111 + .flags = CLK_SET_RATE_PARENT,
1112 + .ops = &clk_regmap_div_ro_ops,
1113 + },
1114 +};
1115 +
1116 +static struct clk_regmap_div nss_cc_xgmac5_ptp_ref_div_clk_src = {
1117 + .reg = 0x28228,
1118 + .shift = 0,
1119 + .width = 4,
1120 + .clkr.hw.init = &(const struct clk_init_data) {
1121 + .name = "nss_cc_xgmac5_ptp_ref_div_clk_src",
1122 + .parent_data = &(const struct clk_parent_data) {
1123 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1124 + },
1125 + .num_parents = 1,
1126 + .flags = CLK_SET_RATE_PARENT,
1127 + .ops = &clk_regmap_div_ro_ops,
1128 + },
1129 +};
1130 +
1131 +static struct clk_branch nss_cc_ce_apb_clk = {
1132 + .halt_reg = 0x2840c,
1133 + .clkr = {
1134 + .enable_reg = 0x2840c,
1135 + .enable_mask = BIT(0),
1136 + .hw.init = &(const struct clk_init_data) {
1137 + .name = "nss_cc_ce_apb_clk",
1138 + .parent_data = &(const struct clk_parent_data) {
1139 + .hw = &nss_cc_ce_clk_src.clkr.hw,
1140 + },
1141 + .num_parents = 1,
1142 + .flags = CLK_SET_RATE_PARENT,
1143 + .ops = &clk_branch2_ops,
1144 + },
1145 + },
1146 +};
1147 +
1148 +static struct clk_branch nss_cc_ce_axi_clk = {
1149 + .halt_reg = 0x28410,
1150 + .halt_check = BRANCH_HALT,
1151 + .clkr = {
1152 + .enable_reg = 0x28410,
1153 + .enable_mask = BIT(0),
1154 + .hw.init = &(const struct clk_init_data) {
1155 + .name = "nss_cc_ce_axi_clk",
1156 + .parent_data = &(const struct clk_parent_data) {
1157 + .hw = &nss_cc_ce_clk_src.clkr.hw,
1158 + },
1159 + .num_parents = 1,
1160 + .flags = CLK_SET_RATE_PARENT,
1161 + .ops = &clk_branch2_ops,
1162 + },
1163 + },
1164 +};
1165 +
1166 +static struct clk_branch nss_cc_clc_axi_clk = {
1167 + .halt_reg = 0x2860c,
1168 + .halt_check = BRANCH_HALT,
1169 + .clkr = {
1170 + .enable_reg = 0x2860c,
1171 + .enable_mask = BIT(0),
1172 + .hw.init = &(const struct clk_init_data) {
1173 + .name = "nss_cc_clc_axi_clk",
1174 + .parent_data = &(const struct clk_parent_data) {
1175 + .hw = &nss_cc_clc_clk_src.clkr.hw,
1176 + },
1177 + .num_parents = 1,
1178 + .flags = CLK_SET_RATE_PARENT,
1179 + .ops = &clk_branch2_ops,
1180 + },
1181 + },
1182 +};
1183 +
1184 +static struct clk_branch nss_cc_crypto_clk = {
1185 + .halt_reg = 0x1601c,
1186 + .halt_check = BRANCH_HALT,
1187 + .clkr = {
1188 + .enable_reg = 0x1601c,
1189 + .enable_mask = BIT(0),
1190 + .hw.init = &(const struct clk_init_data) {
1191 + .name = "nss_cc_crypto_clk",
1192 + .parent_data = &(const struct clk_parent_data) {
1193 + .hw = &nss_cc_crypto_clk_src.clkr.hw,
1194 + },
1195 + .num_parents = 1,
1196 + .flags = CLK_SET_RATE_PARENT,
1197 + .ops = &clk_branch2_ops,
1198 + },
1199 + },
1200 +};
1201 +
1202 +static struct clk_branch nss_cc_crypto_ppe_clk = {
1203 + .halt_reg = 0x28240,
1204 + .halt_check = BRANCH_HALT,
1205 + .clkr = {
1206 + .enable_reg = 0x28240,
1207 + .enable_mask = BIT(0),
1208 + .hw.init = &(const struct clk_init_data) {
1209 + .name = "nss_cc_crypto_ppe_clk",
1210 + .parent_data = &(const struct clk_parent_data) {
1211 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1212 + },
1213 + .num_parents = 1,
1214 + .flags = CLK_SET_RATE_PARENT,
1215 + .ops = &clk_branch2_ops,
1216 + },
1217 + },
1218 +};
1219 +
1220 +static struct clk_branch nss_cc_haq_ahb_clk = {
1221 + .halt_reg = 0x2830c,
1222 + .halt_check = BRANCH_HALT,
1223 + .clkr = {
1224 + .enable_reg = 0x2830c,
1225 + .enable_mask = BIT(0),
1226 + .hw.init = &(const struct clk_init_data) {
1227 + .name = "nss_cc_haq_ahb_clk",
1228 + .parent_data = &(const struct clk_parent_data) {
1229 + .hw = &nss_cc_haq_clk_src.clkr.hw,
1230 + },
1231 + .num_parents = 1,
1232 + .flags = CLK_SET_RATE_PARENT,
1233 + .ops = &clk_branch2_ops,
1234 + },
1235 + },
1236 +};
1237 +
1238 +static struct clk_branch nss_cc_haq_axi_clk = {
1239 + .halt_reg = 0x28310,
1240 + .halt_check = BRANCH_HALT,
1241 + .clkr = {
1242 + .enable_reg = 0x28310,
1243 + .enable_mask = BIT(0),
1244 + .hw.init = &(const struct clk_init_data) {
1245 + .name = "nss_cc_haq_axi_clk",
1246 + .parent_data = &(const struct clk_parent_data) {
1247 + .hw = &nss_cc_haq_clk_src.clkr.hw,
1248 + },
1249 + .num_parents = 1,
1250 + .flags = CLK_SET_RATE_PARENT,
1251 + .ops = &clk_branch2_ops,
1252 + },
1253 + },
1254 +};
1255 +
1256 +static struct clk_branch nss_cc_imem_ahb_clk = {
1257 + .halt_reg = 0xe018,
1258 + .halt_check = BRANCH_HALT,
1259 + .clkr = {
1260 + .enable_reg = 0xe018,
1261 + .enable_mask = BIT(0),
1262 + .hw.init = &(const struct clk_init_data) {
1263 + .name = "nss_cc_imem_ahb_clk",
1264 + .parent_data = &(const struct clk_parent_data) {
1265 + .hw = &nss_cc_cfg_clk_src.clkr.hw,
1266 + },
1267 + .num_parents = 1,
1268 + .flags = CLK_SET_RATE_PARENT,
1269 + .ops = &clk_branch2_ops,
1270 + },
1271 + },
1272 +};
1273 +
1274 +static struct clk_branch nss_cc_imem_qsb_clk = {
1275 + .halt_reg = 0xe010,
1276 + .halt_check = BRANCH_HALT,
1277 + .clkr = {
1278 + .enable_reg = 0xe010,
1279 + .enable_mask = BIT(0),
1280 + .hw.init = &(const struct clk_init_data) {
1281 + .name = "nss_cc_imem_qsb_clk",
1282 + .parent_data = &(const struct clk_parent_data) {
1283 + .hw = &nss_cc_imem_clk_src.clkr.hw,
1284 + },
1285 + .num_parents = 1,
1286 + .flags = CLK_SET_RATE_PARENT,
1287 + .ops = &clk_branch2_ops,
1288 + },
1289 + },
1290 +};
1291 +
1292 +static struct clk_branch nss_cc_nss_csr_clk = {
1293 + .halt_reg = 0x281d0,
1294 + .halt_check = BRANCH_HALT,
1295 + .clkr = {
1296 + .enable_reg = 0x281d0,
1297 + .enable_mask = BIT(0),
1298 + .hw.init = &(const struct clk_init_data) {
1299 + .name = "nss_cc_nss_csr_clk",
1300 + .parent_data = &(const struct clk_parent_data) {
1301 + .hw = &nss_cc_cfg_clk_src.clkr.hw,
1302 + },
1303 + .num_parents = 1,
1304 + .flags = CLK_SET_RATE_PARENT,
1305 + .ops = &clk_branch2_ops,
1306 + },
1307 + },
1308 +};
1309 +
1310 +static struct clk_branch nss_cc_nssnoc_ce_apb_clk = {
1311 + .halt_reg = 0x28414,
1312 + .halt_check = BRANCH_HALT,
1313 + .clkr = {
1314 + .enable_reg = 0x28414,
1315 + .enable_mask = BIT(0),
1316 + .hw.init = &(const struct clk_init_data) {
1317 + .name = "nss_cc_nssnoc_ce_apb_clk",
1318 + .parent_data = &(const struct clk_parent_data) {
1319 + .hw = &nss_cc_ce_clk_src.clkr.hw,
1320 + },
1321 + .num_parents = 1,
1322 + .flags = CLK_SET_RATE_PARENT,
1323 + .ops = &clk_branch2_ops,
1324 + },
1325 + },
1326 +};
1327 +
1328 +static struct clk_branch nss_cc_nssnoc_ce_axi_clk = {
1329 + .halt_reg = 0x28418,
1330 + .halt_check = BRANCH_HALT,
1331 + .clkr = {
1332 + .enable_reg = 0x28418,
1333 + .enable_mask = BIT(0),
1334 + .hw.init = &(const struct clk_init_data) {
1335 + .name = "nss_cc_nssnoc_ce_axi_clk",
1336 + .parent_data = &(const struct clk_parent_data) {
1337 + .hw = &nss_cc_ce_clk_src.clkr.hw,
1338 + },
1339 + .num_parents = 1,
1340 + .flags = CLK_SET_RATE_PARENT,
1341 + .ops = &clk_branch2_ops,
1342 + },
1343 + },
1344 +};
1345 +
1346 +static struct clk_branch nss_cc_nssnoc_clc_axi_clk = {
1347 + .halt_reg = 0x28610,
1348 + .halt_check = BRANCH_HALT,
1349 + .clkr = {
1350 + .enable_reg = 0x28610,
1351 + .enable_mask = BIT(0),
1352 + .hw.init = &(const struct clk_init_data) {
1353 + .name = "nss_cc_nssnoc_clc_axi_clk",
1354 + .parent_data = &(const struct clk_parent_data) {
1355 + .hw = &nss_cc_clc_clk_src.clkr.hw,
1356 + },
1357 + .num_parents = 1,
1358 + .flags = CLK_SET_RATE_PARENT,
1359 + .ops = &clk_branch2_ops,
1360 + },
1361 + },
1362 +};
1363 +
1364 +static struct clk_branch nss_cc_nssnoc_crypto_clk = {
1365 + .halt_reg = 0x16020,
1366 + .halt_check = BRANCH_HALT,
1367 + .clkr = {
1368 + .enable_reg = 0x16020,
1369 + .enable_mask = BIT(0),
1370 + .hw.init = &(const struct clk_init_data) {
1371 + .name = "nss_cc_nssnoc_crypto_clk",
1372 + .parent_data = &(const struct clk_parent_data) {
1373 + .hw = &nss_cc_crypto_clk_src.clkr.hw,
1374 + },
1375 + .num_parents = 1,
1376 + .flags = CLK_SET_RATE_PARENT,
1377 + .ops = &clk_branch2_ops,
1378 + },
1379 + },
1380 +};
1381 +
1382 +static struct clk_branch nss_cc_nssnoc_haq_ahb_clk = {
1383 + .halt_reg = 0x28314,
1384 + .halt_check = BRANCH_HALT,
1385 + .clkr = {
1386 + .enable_reg = 0x28314,
1387 + .enable_mask = BIT(0),
1388 + .hw.init = &(const struct clk_init_data) {
1389 + .name = "nss_cc_nssnoc_haq_ahb_clk",
1390 + .parent_data = &(const struct clk_parent_data) {
1391 + .hw = &nss_cc_haq_clk_src.clkr.hw,
1392 + },
1393 + .num_parents = 1,
1394 + .flags = CLK_SET_RATE_PARENT,
1395 + .ops = &clk_branch2_ops,
1396 + },
1397 + },
1398 +};
1399 +
1400 +static struct clk_branch nss_cc_nssnoc_haq_axi_clk = {
1401 + .halt_reg = 0x28318,
1402 + .halt_check = BRANCH_HALT,
1403 + .clkr = {
1404 + .enable_reg = 0x28318,
1405 + .enable_mask = BIT(0),
1406 + .hw.init = &(const struct clk_init_data) {
1407 + .name = "nss_cc_nssnoc_haq_axi_clk",
1408 + .parent_data = &(const struct clk_parent_data) {
1409 + .hw = &nss_cc_haq_clk_src.clkr.hw,
1410 + },
1411 + .num_parents = 1,
1412 + .flags = CLK_SET_RATE_PARENT,
1413 + .ops = &clk_branch2_ops,
1414 + },
1415 + },
1416 +};
1417 +
1418 +static struct clk_branch nss_cc_nssnoc_imem_ahb_clk = {
1419 + .halt_reg = 0xe01c,
1420 + .halt_check = BRANCH_HALT,
1421 + .clkr = {
1422 + .enable_reg = 0xe01c,
1423 + .enable_mask = BIT(0),
1424 + .hw.init = &(const struct clk_init_data) {
1425 + .name = "nss_cc_nssnoc_imem_ahb_clk",
1426 + .parent_data = &(const struct clk_parent_data) {
1427 + .hw = &nss_cc_cfg_clk_src.clkr.hw,
1428 + },
1429 + .num_parents = 1,
1430 + .flags = CLK_SET_RATE_PARENT,
1431 + .ops = &clk_branch2_ops,
1432 + },
1433 + },
1434 +};
1435 +
1436 +static struct clk_branch nss_cc_nssnoc_imem_qsb_clk = {
1437 + .halt_reg = 0xe014,
1438 + .halt_check = BRANCH_HALT,
1439 + .clkr = {
1440 + .enable_reg = 0xe014,
1441 + .enable_mask = BIT(0),
1442 + .hw.init = &(const struct clk_init_data) {
1443 + .name = "nss_cc_nssnoc_imem_qsb_clk",
1444 + .parent_data = &(const struct clk_parent_data) {
1445 + .hw = &nss_cc_imem_clk_src.clkr.hw,
1446 + },
1447 + .num_parents = 1,
1448 + .flags = CLK_SET_RATE_PARENT,
1449 + .ops = &clk_branch2_ops,
1450 + },
1451 + },
1452 +};
1453 +
1454 +static struct clk_branch nss_cc_nssnoc_nss_csr_clk = {
1455 + .halt_reg = 0x281d4,
1456 + .halt_check = BRANCH_HALT,
1457 + .clkr = {
1458 + .enable_reg = 0x281d4,
1459 + .enable_mask = BIT(0),
1460 + .hw.init = &(const struct clk_init_data) {
1461 + .name = "nss_cc_nssnoc_nss_csr_clk",
1462 + .parent_data = &(const struct clk_parent_data) {
1463 + .hw = &nss_cc_cfg_clk_src.clkr.hw,
1464 + },
1465 + .num_parents = 1,
1466 + .flags = CLK_SET_RATE_PARENT,
1467 + .ops = &clk_branch2_ops,
1468 + },
1469 + },
1470 +};
1471 +
1472 +static struct clk_branch nss_cc_nssnoc_ppe_cfg_clk = {
1473 + .halt_reg = 0x28248,
1474 + .halt_check = BRANCH_HALT,
1475 + .clkr = {
1476 + .enable_reg = 0x28248,
1477 + .enable_mask = BIT(0),
1478 + .hw.init = &(const struct clk_init_data) {
1479 + .name = "nss_cc_nssnoc_ppe_cfg_clk",
1480 + .parent_data = &(const struct clk_parent_data) {
1481 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1482 + },
1483 + .num_parents = 1,
1484 + .flags = CLK_SET_RATE_PARENT,
1485 + .ops = &clk_branch2_ops,
1486 + },
1487 + },
1488 +};
1489 +
1490 +static struct clk_branch nss_cc_nssnoc_ppe_clk = {
1491 + .halt_reg = 0x28244,
1492 + .halt_check = BRANCH_HALT,
1493 + .clkr = {
1494 + .enable_reg = 0x28244,
1495 + .enable_mask = BIT(0),
1496 + .hw.init = &(const struct clk_init_data) {
1497 + .name = "nss_cc_nssnoc_ppe_clk",
1498 + .parent_data = &(const struct clk_parent_data) {
1499 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1500 + },
1501 + .num_parents = 1,
1502 + .flags = CLK_SET_RATE_PARENT,
1503 + .ops = &clk_branch2_ops,
1504 + },
1505 + },
1506 +};
1507 +
1508 +static struct clk_branch nss_cc_nssnoc_ubi32_ahb0_clk = {
1509 + .halt_reg = 0x28788,
1510 + .halt_check = BRANCH_HALT,
1511 + .clkr = {
1512 + .enable_reg = 0x28788,
1513 + .enable_mask = BIT(0),
1514 + .hw.init = &(const struct clk_init_data) {
1515 + .name = "nss_cc_nssnoc_ubi32_ahb0_clk",
1516 + .parent_data = &(const struct clk_parent_data) {
1517 + .hw = &nss_cc_cfg_clk_src.clkr.hw,
1518 + },
1519 + .num_parents = 1,
1520 + .flags = CLK_SET_RATE_PARENT,
1521 + .ops = &clk_branch2_ops,
1522 + },
1523 + },
1524 +};
1525 +
1526 +static struct clk_branch nss_cc_nssnoc_ubi32_axi0_clk = {
1527 + .halt_reg = 0x287a0,
1528 + .halt_check = BRANCH_HALT,
1529 + .clkr = {
1530 + .enable_reg = 0x287a0,
1531 + .enable_mask = BIT(0),
1532 + .hw.init = &(const struct clk_init_data) {
1533 + .name = "nss_cc_nssnoc_ubi32_axi0_clk",
1534 + .parent_data = &(const struct clk_parent_data) {
1535 + .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
1536 + },
1537 + .num_parents = 1,
1538 + .flags = CLK_SET_RATE_PARENT,
1539 + .ops = &clk_branch2_ops,
1540 + },
1541 + },
1542 +};
1543 +
1544 +static struct clk_branch nss_cc_nssnoc_ubi32_int0_ahb_clk = {
1545 + .halt_reg = 0x2878c,
1546 + .halt_check = BRANCH_HALT,
1547 + .clkr = {
1548 + .enable_reg = 0x2878c,
1549 + .enable_mask = BIT(0),
1550 + .hw.init = &(const struct clk_init_data) {
1551 + .name = "nss_cc_nssnoc_ubi32_int0_ahb_clk",
1552 + .parent_data = &(const struct clk_parent_data) {
1553 + .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
1554 + },
1555 + .num_parents = 1,
1556 + .flags = CLK_SET_RATE_PARENT,
1557 + .ops = &clk_branch2_ops,
1558 + },
1559 + },
1560 +};
1561 +
1562 +static struct clk_branch nss_cc_nssnoc_ubi32_nc_axi0_1_clk = {
1563 + .halt_reg = 0x287bc,
1564 + .halt_check = BRANCH_HALT,
1565 + .clkr = {
1566 + .enable_reg = 0x287bc,
1567 + .enable_mask = BIT(0),
1568 + .hw.init = &(const struct clk_init_data) {
1569 + .name = "nss_cc_nssnoc_ubi32_nc_axi0_1_clk",
1570 + .parent_data = &(const struct clk_parent_data) {
1571 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
1572 + },
1573 + .num_parents = 1,
1574 + .flags = CLK_SET_RATE_PARENT,
1575 + .ops = &clk_branch2_ops,
1576 + },
1577 + },
1578 +};
1579 +
1580 +static struct clk_branch nss_cc_nssnoc_ubi32_nc_axi0_clk = {
1581 + .halt_reg = 0x28764,
1582 + .halt_check = BRANCH_HALT,
1583 + .clkr = {
1584 + .enable_reg = 0x28764,
1585 + .enable_mask = BIT(0),
1586 + .hw.init = &(const struct clk_init_data) {
1587 + .name = "nss_cc_nssnoc_ubi32_nc_axi0_clk",
1588 + .parent_data = &(const struct clk_parent_data) {
1589 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
1590 + },
1591 + .num_parents = 1,
1592 + .flags = CLK_SET_RATE_PARENT,
1593 + .ops = &clk_branch2_ops,
1594 + },
1595 + },
1596 +};
1597 +
1598 +static struct clk_branch nss_cc_port1_mac_clk = {
1599 + .halt_reg = 0x2824c,
1600 + .halt_check = BRANCH_HALT,
1601 + .clkr = {
1602 + .enable_reg = 0x2824c,
1603 + .enable_mask = BIT(0),
1604 + .hw.init = &(const struct clk_init_data) {
1605 + .name = "nss_cc_port1_mac_clk",
1606 + .parent_data = &(const struct clk_parent_data) {
1607 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1608 + },
1609 + .num_parents = 1,
1610 + .flags = CLK_SET_RATE_PARENT,
1611 + .ops = &clk_branch2_ops,
1612 + },
1613 + },
1614 +};
1615 +
1616 +static struct clk_branch nss_cc_port1_rx_clk = {
1617 + .halt_reg = 0x281a0,
1618 + .halt_check = BRANCH_HALT,
1619 + .clkr = {
1620 + .enable_reg = 0x281a0,
1621 + .enable_mask = BIT(0),
1622 + .hw.init = &(const struct clk_init_data) {
1623 + .name = "nss_cc_port1_rx_clk",
1624 + .parent_data = &(const struct clk_parent_data) {
1625 + .hw = &nss_cc_port1_rx_div_clk_src.clkr.hw,
1626 + },
1627 + .num_parents = 1,
1628 + .flags = CLK_SET_RATE_PARENT,
1629 + .ops = &clk_branch2_ops,
1630 + },
1631 + },
1632 +};
1633 +
1634 +static struct clk_branch nss_cc_port1_tx_clk = {
1635 + .halt_reg = 0x281a4,
1636 + .halt_check = BRANCH_HALT,
1637 + .clkr = {
1638 + .enable_reg = 0x281a4,
1639 + .enable_mask = BIT(0),
1640 + .hw.init = &(const struct clk_init_data) {
1641 + .name = "nss_cc_port1_tx_clk",
1642 + .parent_data = &(const struct clk_parent_data) {
1643 + .hw = &nss_cc_port1_tx_div_clk_src.clkr.hw,
1644 + },
1645 + .num_parents = 1,
1646 + .flags = CLK_SET_RATE_PARENT,
1647 + .ops = &clk_branch2_ops,
1648 + },
1649 + },
1650 +};
1651 +
1652 +static struct clk_branch nss_cc_port2_mac_clk = {
1653 + .halt_reg = 0x28250,
1654 + .halt_check = BRANCH_HALT,
1655 + .clkr = {
1656 + .enable_reg = 0x28250,
1657 + .enable_mask = BIT(0),
1658 + .hw.init = &(const struct clk_init_data) {
1659 + .name = "nss_cc_port2_mac_clk",
1660 + .parent_data = &(const struct clk_parent_data) {
1661 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1662 + },
1663 + .num_parents = 1,
1664 + .flags = CLK_SET_RATE_PARENT,
1665 + .ops = &clk_branch2_ops,
1666 + },
1667 + },
1668 +};
1669 +
1670 +static struct clk_branch nss_cc_port2_rx_clk = {
1671 + .halt_reg = 0x281a8,
1672 + .halt_check = BRANCH_HALT,
1673 + .clkr = {
1674 + .enable_reg = 0x281a8,
1675 + .enable_mask = BIT(0),
1676 + .hw.init = &(const struct clk_init_data) {
1677 + .name = "nss_cc_port2_rx_clk",
1678 + .parent_data = &(const struct clk_parent_data) {
1679 + .hw = &nss_cc_port2_rx_div_clk_src.clkr.hw,
1680 + },
1681 + .num_parents = 1,
1682 + .flags = CLK_SET_RATE_PARENT,
1683 + .ops = &clk_branch2_ops,
1684 + },
1685 + },
1686 +};
1687 +
1688 +static struct clk_branch nss_cc_port2_tx_clk = {
1689 + .halt_reg = 0x281ac,
1690 + .halt_check = BRANCH_HALT,
1691 + .clkr = {
1692 + .enable_reg = 0x281ac,
1693 + .enable_mask = BIT(0),
1694 + .hw.init = &(const struct clk_init_data) {
1695 + .name = "nss_cc_port2_tx_clk",
1696 + .parent_data = &(const struct clk_parent_data) {
1697 + .hw = &nss_cc_port2_tx_div_clk_src.clkr.hw,
1698 + },
1699 + .num_parents = 1,
1700 + .flags = CLK_SET_RATE_PARENT,
1701 + .ops = &clk_branch2_ops,
1702 + },
1703 + },
1704 +};
1705 +
1706 +static struct clk_branch nss_cc_port3_mac_clk = {
1707 + .halt_reg = 0x28254,
1708 + .halt_check = BRANCH_HALT,
1709 + .clkr = {
1710 + .enable_reg = 0x28254,
1711 + .enable_mask = BIT(0),
1712 + .hw.init = &(const struct clk_init_data) {
1713 + .name = "nss_cc_port3_mac_clk",
1714 + .parent_data = &(const struct clk_parent_data) {
1715 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1716 + },
1717 + .num_parents = 1,
1718 + .flags = CLK_SET_RATE_PARENT,
1719 + .ops = &clk_branch2_ops,
1720 + },
1721 + },
1722 +};
1723 +
1724 +static struct clk_branch nss_cc_port3_rx_clk = {
1725 + .halt_reg = 0x281b0,
1726 + .halt_check = BRANCH_HALT,
1727 + .clkr = {
1728 + .enable_reg = 0x281b0,
1729 + .enable_mask = BIT(0),
1730 + .hw.init = &(const struct clk_init_data) {
1731 + .name = "nss_cc_port3_rx_clk",
1732 + .parent_data = &(const struct clk_parent_data) {
1733 + .hw = &nss_cc_port3_rx_div_clk_src.clkr.hw,
1734 + },
1735 + .num_parents = 1,
1736 + .flags = CLK_SET_RATE_PARENT,
1737 + .ops = &clk_branch2_ops,
1738 + },
1739 + },
1740 +};
1741 +
1742 +static struct clk_branch nss_cc_port3_tx_clk = {
1743 + .halt_reg = 0x281b4,
1744 + .halt_check = BRANCH_HALT,
1745 + .clkr = {
1746 + .enable_reg = 0x281b4,
1747 + .enable_mask = BIT(0),
1748 + .hw.init = &(const struct clk_init_data) {
1749 + .name = "nss_cc_port3_tx_clk",
1750 + .parent_data = &(const struct clk_parent_data) {
1751 + .hw = &nss_cc_port3_tx_div_clk_src.clkr.hw,
1752 + },
1753 + .num_parents = 1,
1754 + .flags = CLK_SET_RATE_PARENT,
1755 + .ops = &clk_branch2_ops,
1756 + },
1757 + },
1758 +};
1759 +
1760 +static struct clk_branch nss_cc_port4_mac_clk = {
1761 + .halt_reg = 0x28258,
1762 + .halt_check = BRANCH_HALT,
1763 + .clkr = {
1764 + .enable_reg = 0x28258,
1765 + .enable_mask = BIT(0),
1766 + .hw.init = &(const struct clk_init_data) {
1767 + .name = "nss_cc_port4_mac_clk",
1768 + .parent_data = &(const struct clk_parent_data) {
1769 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1770 + },
1771 + .num_parents = 1,
1772 + .flags = CLK_SET_RATE_PARENT,
1773 + .ops = &clk_branch2_ops,
1774 + },
1775 + },
1776 +};
1777 +
1778 +static struct clk_branch nss_cc_port4_rx_clk = {
1779 + .halt_reg = 0x281b8,
1780 + .halt_check = BRANCH_HALT,
1781 + .clkr = {
1782 + .enable_reg = 0x281b8,
1783 + .enable_mask = BIT(0),
1784 + .hw.init = &(const struct clk_init_data) {
1785 + .name = "nss_cc_port4_rx_clk",
1786 + .parent_data = &(const struct clk_parent_data) {
1787 + .hw = &nss_cc_port4_rx_div_clk_src.clkr.hw,
1788 + },
1789 + .num_parents = 1,
1790 + .flags = CLK_SET_RATE_PARENT,
1791 + .ops = &clk_branch2_ops,
1792 + },
1793 + },
1794 +};
1795 +
1796 +static struct clk_branch nss_cc_port4_tx_clk = {
1797 + .halt_reg = 0x281bc,
1798 + .halt_check = BRANCH_HALT,
1799 + .clkr = {
1800 + .enable_reg = 0x281bc,
1801 + .enable_mask = BIT(0),
1802 + .hw.init = &(const struct clk_init_data) {
1803 + .name = "nss_cc_port4_tx_clk",
1804 + .parent_data = &(const struct clk_parent_data) {
1805 + .hw = &nss_cc_port4_tx_div_clk_src.clkr.hw,
1806 + },
1807 + .num_parents = 1,
1808 + .flags = CLK_SET_RATE_PARENT,
1809 + .ops = &clk_branch2_ops,
1810 + },
1811 + },
1812 +};
1813 +
1814 +static struct clk_branch nss_cc_port5_mac_clk = {
1815 + .halt_reg = 0x2825c,
1816 + .halt_check = BRANCH_HALT,
1817 + .clkr = {
1818 + .enable_reg = 0x2825c,
1819 + .enable_mask = BIT(0),
1820 + .hw.init = &(const struct clk_init_data) {
1821 + .name = "nss_cc_port5_mac_clk",
1822 + .parent_data = &(const struct clk_parent_data) {
1823 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1824 + },
1825 + .num_parents = 1,
1826 + .flags = CLK_SET_RATE_PARENT,
1827 + .ops = &clk_branch2_ops,
1828 + },
1829 + },
1830 +};
1831 +
1832 +static struct clk_branch nss_cc_port5_rx_clk = {
1833 + .halt_reg = 0x281c0,
1834 + .halt_check = BRANCH_HALT,
1835 + .clkr = {
1836 + .enable_reg = 0x281c0,
1837 + .enable_mask = BIT(0),
1838 + .hw.init = &(const struct clk_init_data) {
1839 + .name = "nss_cc_port5_rx_clk",
1840 + .parent_data = &(const struct clk_parent_data) {
1841 + .hw = &nss_cc_port5_rx_div_clk_src.clkr.hw,
1842 + },
1843 + .num_parents = 1,
1844 + .flags = CLK_SET_RATE_PARENT,
1845 + .ops = &clk_branch2_ops,
1846 + },
1847 + },
1848 +};
1849 +
1850 +static struct clk_branch nss_cc_port5_tx_clk = {
1851 + .halt_reg = 0x281c4,
1852 + .halt_check = BRANCH_HALT,
1853 + .clkr = {
1854 + .enable_reg = 0x281c4,
1855 + .enable_mask = BIT(0),
1856 + .hw.init = &(const struct clk_init_data) {
1857 + .name = "nss_cc_port5_tx_clk",
1858 + .parent_data = &(const struct clk_parent_data) {
1859 + .hw = &nss_cc_port5_tx_div_clk_src.clkr.hw,
1860 + },
1861 + .num_parents = 1,
1862 + .flags = CLK_SET_RATE_PARENT,
1863 + .ops = &clk_branch2_ops,
1864 + },
1865 + },
1866 +};
1867 +
1868 +static struct clk_branch nss_cc_port6_mac_clk = {
1869 + .halt_reg = 0x28260,
1870 + .halt_check = BRANCH_HALT,
1871 + .clkr = {
1872 + .enable_reg = 0x28260,
1873 + .enable_mask = BIT(0),
1874 + .hw.init = &(const struct clk_init_data) {
1875 + .name = "nss_cc_port6_mac_clk",
1876 + .parent_data = &(const struct clk_parent_data) {
1877 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1878 + },
1879 + .num_parents = 1,
1880 + .flags = CLK_SET_RATE_PARENT,
1881 + .ops = &clk_branch2_ops,
1882 + },
1883 + },
1884 +};
1885 +
1886 +static struct clk_branch nss_cc_port6_rx_clk = {
1887 + .halt_reg = 0x281c8,
1888 + .halt_check = BRANCH_HALT,
1889 + .clkr = {
1890 + .enable_reg = 0x281c8,
1891 + .enable_mask = BIT(0),
1892 + .hw.init = &(const struct clk_init_data) {
1893 + .name = "nss_cc_port6_rx_clk",
1894 + .parent_data = &(const struct clk_parent_data) {
1895 + .hw = &nss_cc_port6_rx_div_clk_src.clkr.hw,
1896 + },
1897 + .num_parents = 1,
1898 + .flags = CLK_SET_RATE_PARENT,
1899 + .ops = &clk_branch2_ops,
1900 + },
1901 + },
1902 +};
1903 +
1904 +static struct clk_branch nss_cc_port6_tx_clk = {
1905 + .halt_reg = 0x281cc,
1906 + .halt_check = BRANCH_HALT,
1907 + .clkr = {
1908 + .enable_reg = 0x281cc,
1909 + .enable_mask = BIT(0),
1910 + .hw.init = &(const struct clk_init_data) {
1911 + .name = "nss_cc_port6_tx_clk",
1912 + .parent_data = &(const struct clk_parent_data) {
1913 + .hw = &nss_cc_port6_tx_div_clk_src.clkr.hw,
1914 + },
1915 + .num_parents = 1,
1916 + .flags = CLK_SET_RATE_PARENT,
1917 + .ops = &clk_branch2_ops,
1918 + },
1919 + },
1920 +};
1921 +
1922 +static struct clk_branch nss_cc_ppe_edma_cfg_clk = {
1923 + .halt_reg = 0x2823c,
1924 + .halt_check = BRANCH_HALT,
1925 + .clkr = {
1926 + .enable_reg = 0x2823c,
1927 + .enable_mask = BIT(0),
1928 + .hw.init = &(const struct clk_init_data) {
1929 + .name = "nss_cc_ppe_edma_cfg_clk",
1930 + .parent_data = &(const struct clk_parent_data) {
1931 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1932 + },
1933 + .num_parents = 1,
1934 + .flags = CLK_SET_RATE_PARENT,
1935 + .ops = &clk_branch2_ops,
1936 + },
1937 + },
1938 +};
1939 +
1940 +static struct clk_branch nss_cc_ppe_edma_clk = {
1941 + .halt_reg = 0x28238,
1942 + .halt_check = BRANCH_HALT,
1943 + .clkr = {
1944 + .enable_reg = 0x28238,
1945 + .enable_mask = BIT(0),
1946 + .hw.init = &(const struct clk_init_data) {
1947 + .name = "nss_cc_ppe_edma_clk",
1948 + .parent_data = &(const struct clk_parent_data) {
1949 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1950 + },
1951 + .num_parents = 1,
1952 + .flags = CLK_SET_RATE_PARENT,
1953 + .ops = &clk_branch2_ops,
1954 + },
1955 + },
1956 +};
1957 +
1958 +static struct clk_branch nss_cc_ppe_switch_btq_clk = {
1959 + .halt_reg = 0x2827c,
1960 + .halt_check = BRANCH_HALT,
1961 + .clkr = {
1962 + .enable_reg = 0x2827c,
1963 + .enable_mask = BIT(0),
1964 + .hw.init = &(const struct clk_init_data) {
1965 + .name = "nss_cc_ppe_switch_btq_clk",
1966 + .parent_data = &(const struct clk_parent_data) {
1967 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1968 + },
1969 + .num_parents = 1,
1970 + .flags = CLK_SET_RATE_PARENT,
1971 + .ops = &clk_branch2_ops,
1972 + },
1973 + },
1974 +};
1975 +
1976 +static struct clk_branch nss_cc_ppe_switch_cfg_clk = {
1977 + .halt_reg = 0x28234,
1978 + .halt_check = BRANCH_HALT,
1979 + .clkr = {
1980 + .enable_reg = 0x28234,
1981 + .enable_mask = BIT(0),
1982 + .hw.init = &(const struct clk_init_data) {
1983 + .name = "nss_cc_ppe_switch_cfg_clk",
1984 + .parent_data = &(const struct clk_parent_data) {
1985 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1986 + },
1987 + .num_parents = 1,
1988 + .flags = CLK_SET_RATE_PARENT,
1989 + .ops = &clk_branch2_ops,
1990 + },
1991 + },
1992 +};
1993 +
1994 +static struct clk_branch nss_cc_ppe_switch_clk = {
1995 + .halt_reg = 0x28230,
1996 + .halt_check = BRANCH_HALT,
1997 + .clkr = {
1998 + .enable_reg = 0x28230,
1999 + .enable_mask = BIT(0),
2000 + .hw.init = &(const struct clk_init_data) {
2001 + .name = "nss_cc_ppe_switch_clk",
2002 + .parent_data = &(const struct clk_parent_data) {
2003 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
2004 + },
2005 + .num_parents = 1,
2006 + .flags = CLK_SET_RATE_PARENT,
2007 + .ops = &clk_branch2_ops,
2008 + },
2009 + },
2010 +};
2011 +
2012 +static struct clk_branch nss_cc_ppe_switch_ipe_clk = {
2013 + .halt_reg = 0x2822c,
2014 + .halt_check = BRANCH_HALT,
2015 + .clkr = {
2016 + .enable_reg = 0x2822c,
2017 + .enable_mask = BIT(0),
2018 + .hw.init = &(const struct clk_init_data) {
2019 + .name = "nss_cc_ppe_switch_ipe_clk",
2020 + .parent_data = &(const struct clk_parent_data) {
2021 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
2022 + },
2023 + .num_parents = 1,
2024 + .flags = CLK_SET_RATE_PARENT,
2025 + .ops = &clk_branch2_ops,
2026 + },
2027 + },
2028 +};
2029 +
2030 +static struct clk_branch nss_cc_ubi32_ahb0_clk = {
2031 + .halt_reg = 0x28768,
2032 + .halt_check = BRANCH_HALT,
2033 + .clkr = {
2034 + .enable_reg = 0x28768,
2035 + .enable_mask = BIT(0),
2036 + .hw.init = &(const struct clk_init_data) {
2037 + .name = "nss_cc_ubi32_ahb0_clk",
2038 + .parent_data = &(const struct clk_parent_data) {
2039 + .hw = &nss_cc_cfg_clk_src.clkr.hw,
2040 + },
2041 + .num_parents = 1,
2042 + .flags = CLK_SET_RATE_PARENT,
2043 + .ops = &clk_branch2_ops,
2044 + },
2045 + },
2046 +};
2047 +
2048 +static struct clk_branch nss_cc_ubi32_ahb1_clk = {
2049 + .halt_reg = 0x28770,
2050 + .halt_check = BRANCH_HALT,
2051 + .clkr = {
2052 + .enable_reg = 0x28770,
2053 + .enable_mask = BIT(0),
2054 + .hw.init = &(const struct clk_init_data) {
2055 + .name = "nss_cc_ubi32_ahb1_clk",
2056 + .parent_data = &(const struct clk_parent_data) {
2057 + .hw = &nss_cc_cfg_clk_src.clkr.hw,
2058 + },
2059 + .num_parents = 1,
2060 + .flags = CLK_SET_RATE_PARENT,
2061 + .ops = &clk_branch2_ops,
2062 + },
2063 + },
2064 +};
2065 +
2066 +static struct clk_branch nss_cc_ubi32_ahb2_clk = {
2067 + .halt_reg = 0x28778,
2068 + .halt_check = BRANCH_HALT,
2069 + .clkr = {
2070 + .enable_reg = 0x28778,
2071 + .enable_mask = BIT(0),
2072 + .hw.init = &(const struct clk_init_data) {
2073 + .name = "nss_cc_ubi32_ahb2_clk",
2074 + .parent_data = &(const struct clk_parent_data) {
2075 + .hw = &nss_cc_cfg_clk_src.clkr.hw,
2076 + },
2077 + .num_parents = 1,
2078 + .flags = CLK_SET_RATE_PARENT,
2079 + .ops = &clk_branch2_ops,
2080 + },
2081 + },
2082 +};
2083 +
2084 +static struct clk_branch nss_cc_ubi32_ahb3_clk = {
2085 + .halt_reg = 0x28780,
2086 + .halt_check = BRANCH_HALT,
2087 + .clkr = {
2088 + .enable_reg = 0x28780,
2089 + .enable_mask = BIT(0),
2090 + .hw.init = &(const struct clk_init_data) {
2091 + .name = "nss_cc_ubi32_ahb3_clk",
2092 + .parent_data = &(const struct clk_parent_data) {
2093 + .hw = &nss_cc_cfg_clk_src.clkr.hw,
2094 + },
2095 + .num_parents = 1,
2096 + .flags = CLK_SET_RATE_PARENT,
2097 + .ops = &clk_branch2_ops,
2098 + },
2099 + },
2100 +};
2101 +
2102 +static struct clk_branch nss_cc_ubi32_axi0_clk = {
2103 + .halt_reg = 0x28790,
2104 + .halt_check = BRANCH_HALT,
2105 + .clkr = {
2106 + .enable_reg = 0x28790,
2107 + .enable_mask = BIT(0),
2108 + .hw.init = &(const struct clk_init_data) {
2109 + .name = "nss_cc_ubi32_axi0_clk",
2110 + .parent_data = &(const struct clk_parent_data) {
2111 + .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
2112 + },
2113 + .num_parents = 1,
2114 + .flags = CLK_SET_RATE_PARENT,
2115 + .ops = &clk_branch2_ops,
2116 + },
2117 + },
2118 +};
2119 +
2120 +static struct clk_branch nss_cc_ubi32_axi1_clk = {
2121 + .halt_reg = 0x28794,
2122 + .halt_check = BRANCH_HALT,
2123 + .clkr = {
2124 + .enable_reg = 0x28794,
2125 + .enable_mask = BIT(0),
2126 + .hw.init = &(const struct clk_init_data) {
2127 + .name = "nss_cc_ubi32_axi1_clk",
2128 + .parent_data = &(const struct clk_parent_data) {
2129 + .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
2130 + },
2131 + .num_parents = 1,
2132 + .flags = CLK_SET_RATE_PARENT,
2133 + .ops = &clk_branch2_ops,
2134 + },
2135 + },
2136 +};
2137 +
2138 +static struct clk_branch nss_cc_ubi32_axi2_clk = {
2139 + .halt_reg = 0x28798,
2140 + .halt_check = BRANCH_HALT,
2141 + .clkr = {
2142 + .enable_reg = 0x28798,
2143 + .enable_mask = BIT(0),
2144 + .hw.init = &(const struct clk_init_data) {
2145 + .name = "nss_cc_ubi32_axi2_clk",
2146 + .parent_data = &(const struct clk_parent_data) {
2147 + .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
2148 + },
2149 + .num_parents = 1,
2150 + .flags = CLK_SET_RATE_PARENT,
2151 + .ops = &clk_branch2_ops,
2152 + },
2153 + },
2154 +};
2155 +
2156 +static struct clk_branch nss_cc_ubi32_axi3_clk = {
2157 + .halt_reg = 0x2879c,
2158 + .halt_check = BRANCH_HALT,
2159 + .clkr = {
2160 + .enable_reg = 0x2879c,
2161 + .enable_mask = BIT(0),
2162 + .hw.init = &(const struct clk_init_data) {
2163 + .name = "nss_cc_ubi32_axi3_clk",
2164 + .parent_data = &(const struct clk_parent_data) {
2165 + .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
2166 + },
2167 + .num_parents = 1,
2168 + .flags = CLK_SET_RATE_PARENT,
2169 + .ops = &clk_branch2_ops,
2170 + },
2171 + },
2172 +};
2173 +
2174 +static struct clk_branch nss_cc_ubi32_core0_clk = {
2175 + .halt_reg = 0x28734,
2176 + .halt_check = BRANCH_HALT,
2177 + .clkr = {
2178 + .enable_reg = 0x28734,
2179 + .enable_mask = BIT(0),
2180 + .hw.init = &(const struct clk_init_data) {
2181 + .name = "nss_cc_ubi32_core0_clk",
2182 + .parent_data = &(const struct clk_parent_data) {
2183 + .hw = &nss_cc_ubi0_div_clk_src.clkr.hw,
2184 + },
2185 + .num_parents = 1,
2186 + .flags = CLK_SET_RATE_PARENT,
2187 + .ops = &clk_branch2_ops,
2188 + },
2189 + },
2190 +};
2191 +
2192 +static struct clk_branch nss_cc_ubi32_core1_clk = {
2193 + .halt_reg = 0x28738,
2194 + .halt_check = BRANCH_HALT,
2195 + .clkr = {
2196 + .enable_reg = 0x28738,
2197 + .enable_mask = BIT(0),
2198 + .hw.init = &(const struct clk_init_data) {
2199 + .name = "nss_cc_ubi32_core1_clk",
2200 + .parent_data = &(const struct clk_parent_data) {
2201 + .hw = &nss_cc_ubi1_div_clk_src.clkr.hw,
2202 + },
2203 + .num_parents = 1,
2204 + .flags = CLK_SET_RATE_PARENT,
2205 + .ops = &clk_branch2_ops,
2206 + },
2207 + },
2208 +};
2209 +
2210 +static struct clk_branch nss_cc_ubi32_core2_clk = {
2211 + .halt_reg = 0x2873c,
2212 + .halt_check = BRANCH_HALT,
2213 + .clkr = {
2214 + .enable_reg = 0x2873c,
2215 + .enable_mask = BIT(0),
2216 + .hw.init = &(const struct clk_init_data) {
2217 + .name = "nss_cc_ubi32_core2_clk",
2218 + .parent_data = &(const struct clk_parent_data) {
2219 + .hw = &nss_cc_ubi2_div_clk_src.clkr.hw,
2220 + },
2221 + .num_parents = 1,
2222 + .flags = CLK_SET_RATE_PARENT,
2223 + .ops = &clk_branch2_ops,
2224 + },
2225 + },
2226 +};
2227 +
2228 +static struct clk_branch nss_cc_ubi32_core3_clk = {
2229 + .halt_reg = 0x28740,
2230 + .halt_check = BRANCH_HALT,
2231 + .clkr = {
2232 + .enable_reg = 0x28740,
2233 + .enable_mask = BIT(0),
2234 + .hw.init = &(const struct clk_init_data) {
2235 + .name = "nss_cc_ubi32_core3_clk",
2236 + .parent_data = &(const struct clk_parent_data) {
2237 + .hw = &nss_cc_ubi3_div_clk_src.clkr.hw,
2238 + },
2239 + .num_parents = 1,
2240 + .flags = CLK_SET_RATE_PARENT,
2241 + .ops = &clk_branch2_ops,
2242 + },
2243 + },
2244 +};
2245 +
2246 +static struct clk_branch nss_cc_ubi32_intr0_ahb_clk = {
2247 + .halt_reg = 0x2876c,
2248 + .halt_check = BRANCH_HALT,
2249 + .clkr = {
2250 + .enable_reg = 0x2876c,
2251 + .enable_mask = BIT(0),
2252 + .hw.init = &(const struct clk_init_data) {
2253 + .name = "nss_cc_ubi32_intr0_ahb_clk",
2254 + .parent_data = &(const struct clk_parent_data) {
2255 + .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
2256 + },
2257 + .num_parents = 1,
2258 + .flags = CLK_SET_RATE_PARENT,
2259 + .ops = &clk_branch2_ops,
2260 + },
2261 + },
2262 +};
2263 +
2264 +static struct clk_branch nss_cc_ubi32_intr1_ahb_clk = {
2265 + .halt_reg = 0x28774,
2266 + .halt_check = BRANCH_HALT,
2267 + .clkr = {
2268 + .enable_reg = 0x28774,
2269 + .enable_mask = BIT(0),
2270 + .hw.init = &(const struct clk_init_data) {
2271 + .name = "nss_cc_ubi32_intr1_ahb_clk",
2272 + .parent_data = &(const struct clk_parent_data) {
2273 + .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
2274 + },
2275 + .num_parents = 1,
2276 + .flags = CLK_SET_RATE_PARENT,
2277 + .ops = &clk_branch2_ops,
2278 + },
2279 + },
2280 +};
2281 +
2282 +static struct clk_branch nss_cc_ubi32_intr2_ahb_clk = {
2283 + .halt_reg = 0x2877c,
2284 + .halt_check = BRANCH_HALT,
2285 + .clkr = {
2286 + .enable_reg = 0x2877c,
2287 + .enable_mask = BIT(0),
2288 + .hw.init = &(const struct clk_init_data) {
2289 + .name = "nss_cc_ubi32_intr2_ahb_clk",
2290 + .parent_data = &(const struct clk_parent_data) {
2291 + .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
2292 + },
2293 + .num_parents = 1,
2294 + .flags = CLK_SET_RATE_PARENT,
2295 + .ops = &clk_branch2_ops,
2296 + },
2297 + },
2298 +};
2299 +
2300 +static struct clk_branch nss_cc_ubi32_intr3_ahb_clk = {
2301 + .halt_reg = 0x28784,
2302 + .halt_check = BRANCH_HALT,
2303 + .clkr = {
2304 + .enable_reg = 0x28784,
2305 + .enable_mask = BIT(0),
2306 + .hw.init = &(const struct clk_init_data) {
2307 + .name = "nss_cc_ubi32_intr3_ahb_clk",
2308 + .parent_data = &(const struct clk_parent_data) {
2309 + .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
2310 + },
2311 + .num_parents = 1,
2312 + .flags = CLK_SET_RATE_PARENT,
2313 + .ops = &clk_branch2_ops,
2314 + },
2315 + },
2316 +};
2317 +
2318 +static struct clk_branch nss_cc_ubi32_nc_axi0_clk = {
2319 + .halt_reg = 0x28744,
2320 + .halt_check = BRANCH_HALT,
2321 + .clkr = {
2322 + .enable_reg = 0x28744,
2323 + .enable_mask = BIT(0),
2324 + .hw.init = &(const struct clk_init_data) {
2325 + .name = "nss_cc_ubi32_nc_axi0_clk",
2326 + .parent_data = &(const struct clk_parent_data) {
2327 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2328 + },
2329 + .num_parents = 1,
2330 + .flags = CLK_SET_RATE_PARENT,
2331 + .ops = &clk_branch2_ops,
2332 + },
2333 + },
2334 +};
2335 +
2336 +static struct clk_branch nss_cc_ubi32_nc_axi1_clk = {
2337 + .halt_reg = 0x2874c,
2338 + .halt_check = BRANCH_HALT,
2339 + .clkr = {
2340 + .enable_reg = 0x2874c,
2341 + .enable_mask = BIT(0),
2342 + .hw.init = &(const struct clk_init_data) {
2343 + .name = "nss_cc_ubi32_nc_axi1_clk",
2344 + .parent_data = &(const struct clk_parent_data) {
2345 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2346 + },
2347 + .num_parents = 1,
2348 + .flags = CLK_SET_RATE_PARENT,
2349 + .ops = &clk_branch2_ops,
2350 + },
2351 + },
2352 +};
2353 +
2354 +static struct clk_branch nss_cc_ubi32_nc_axi2_clk = {
2355 + .halt_reg = 0x28754,
2356 + .halt_check = BRANCH_HALT,
2357 + .clkr = {
2358 + .enable_reg = 0x28754,
2359 + .enable_mask = BIT(0),
2360 + .hw.init = &(const struct clk_init_data) {
2361 + .name = "nss_cc_ubi32_nc_axi2_clk",
2362 + .parent_data = &(const struct clk_parent_data) {
2363 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2364 + },
2365 + .num_parents = 1,
2366 + .flags = CLK_SET_RATE_PARENT,
2367 + .ops = &clk_branch2_ops,
2368 + },
2369 + },
2370 +};
2371 +
2372 +static struct clk_branch nss_cc_ubi32_nc_axi3_clk = {
2373 + .halt_reg = 0x2875c,
2374 + .halt_check = BRANCH_HALT,
2375 + .clkr = {
2376 + .enable_reg = 0x2875c,
2377 + .enable_mask = BIT(0),
2378 + .hw.init = &(const struct clk_init_data) {
2379 + .name = "nss_cc_ubi32_nc_axi3_clk",
2380 + .parent_data = &(const struct clk_parent_data) {
2381 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2382 + },
2383 + .num_parents = 1,
2384 + .flags = CLK_SET_RATE_PARENT,
2385 + .ops = &clk_branch2_ops,
2386 + },
2387 + },
2388 +};
2389 +
2390 +static struct clk_branch nss_cc_ubi32_utcm0_clk = {
2391 + .halt_reg = 0x28748,
2392 + .halt_check = BRANCH_HALT,
2393 + .clkr = {
2394 + .enable_reg = 0x28748,
2395 + .enable_mask = BIT(0),
2396 + .hw.init = &(const struct clk_init_data) {
2397 + .name = "nss_cc_ubi32_utcm0_clk",
2398 + .parent_data = &(const struct clk_parent_data) {
2399 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2400 + },
2401 + .num_parents = 1,
2402 + .flags = CLK_SET_RATE_PARENT,
2403 + .ops = &clk_branch2_ops,
2404 + },
2405 + },
2406 +};
2407 +
2408 +static struct clk_branch nss_cc_ubi32_utcm1_clk = {
2409 + .halt_reg = 0x28750,
2410 + .halt_check = BRANCH_HALT,
2411 + .clkr = {
2412 + .enable_reg = 0x28750,
2413 + .enable_mask = BIT(0),
2414 + .hw.init = &(const struct clk_init_data) {
2415 + .name = "nss_cc_ubi32_utcm1_clk",
2416 + .parent_data = &(const struct clk_parent_data) {
2417 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2418 + },
2419 + .num_parents = 1,
2420 + .flags = CLK_SET_RATE_PARENT,
2421 + .ops = &clk_branch2_ops,
2422 + },
2423 + },
2424 +};
2425 +
2426 +static struct clk_branch nss_cc_ubi32_utcm2_clk = {
2427 + .halt_reg = 0x28758,
2428 + .halt_check = BRANCH_HALT,
2429 + .clkr = {
2430 + .enable_reg = 0x28758,
2431 + .enable_mask = BIT(0),
2432 + .hw.init = &(const struct clk_init_data) {
2433 + .name = "nss_cc_ubi32_utcm2_clk",
2434 + .parent_data = &(const struct clk_parent_data) {
2435 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2436 + },
2437 + .num_parents = 1,
2438 + .flags = CLK_SET_RATE_PARENT,
2439 + .ops = &clk_branch2_ops,
2440 + },
2441 + },
2442 +};
2443 +
2444 +static struct clk_branch nss_cc_ubi32_utcm3_clk = {
2445 + .halt_reg = 0x28760,
2446 + .halt_check = BRANCH_HALT,
2447 + .clkr = {
2448 + .enable_reg = 0x28760,
2449 + .enable_mask = BIT(0),
2450 + .hw.init = &(const struct clk_init_data) {
2451 + .name = "nss_cc_ubi32_utcm3_clk",
2452 + .parent_data = &(const struct clk_parent_data) {
2453 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2454 + },
2455 + .num_parents = 1,
2456 + .flags = CLK_SET_RATE_PARENT,
2457 + .ops = &clk_branch2_ops,
2458 + },
2459 + },
2460 +};
2461 +
2462 +static struct clk_branch nss_cc_uniphy_port1_rx_clk = {
2463 + .halt_reg = 0x28904,
2464 + .halt_check = BRANCH_HALT,
2465 + .clkr = {
2466 + .enable_reg = 0x28904,
2467 + .enable_mask = BIT(0),
2468 + .hw.init = &(const struct clk_init_data) {
2469 + .name = "nss_cc_uniphy_port1_rx_clk",
2470 + .parent_data = &(const struct clk_parent_data) {
2471 + .hw = &nss_cc_port1_rx_div_clk_src.clkr.hw,
2472 + },
2473 + .num_parents = 1,
2474 + .flags = CLK_SET_RATE_PARENT,
2475 + .ops = &clk_branch2_ops,
2476 + },
2477 + },
2478 +};
2479 +
2480 +static struct clk_branch nss_cc_uniphy_port1_tx_clk = {
2481 + .halt_reg = 0x28908,
2482 + .halt_check = BRANCH_HALT,
2483 + .clkr = {
2484 + .enable_reg = 0x28908,
2485 + .enable_mask = BIT(0),
2486 + .hw.init = &(const struct clk_init_data) {
2487 + .name = "nss_cc_uniphy_port1_tx_clk",
2488 + .parent_data = &(const struct clk_parent_data) {
2489 + .hw = &nss_cc_port1_tx_div_clk_src.clkr.hw,
2490 + },
2491 + .num_parents = 1,
2492 + .flags = CLK_SET_RATE_PARENT,
2493 + .ops = &clk_branch2_ops,
2494 + },
2495 + },
2496 +};
2497 +
2498 +static struct clk_branch nss_cc_uniphy_port2_rx_clk = {
2499 + .halt_reg = 0x2890c,
2500 + .halt_check = BRANCH_HALT,
2501 + .clkr = {
2502 + .enable_reg = 0x2890c,
2503 + .enable_mask = BIT(0),
2504 + .hw.init = &(const struct clk_init_data) {
2505 + .name = "nss_cc_uniphy_port2_rx_clk",
2506 + .parent_data = &(const struct clk_parent_data) {
2507 + .hw = &nss_cc_port2_rx_div_clk_src.clkr.hw,
2508 + },
2509 + .num_parents = 1,
2510 + .flags = CLK_SET_RATE_PARENT,
2511 + .ops = &clk_branch2_ops,
2512 + },
2513 + },
2514 +};
2515 +
2516 +static struct clk_branch nss_cc_uniphy_port2_tx_clk = {
2517 + .halt_reg = 0x28910,
2518 + .halt_check = BRANCH_HALT,
2519 + .clkr = {
2520 + .enable_reg = 0x28910,
2521 + .enable_mask = BIT(0),
2522 + .hw.init = &(const struct clk_init_data) {
2523 + .name = "nss_cc_uniphy_port2_tx_clk",
2524 + .parent_data = &(const struct clk_parent_data) {
2525 + .hw = &nss_cc_port2_tx_div_clk_src.clkr.hw,
2526 + },
2527 + .num_parents = 1,
2528 + .flags = CLK_SET_RATE_PARENT,
2529 + .ops = &clk_branch2_ops,
2530 + },
2531 + },
2532 +};
2533 +
2534 +static struct clk_branch nss_cc_uniphy_port3_rx_clk = {
2535 + .halt_reg = 0x28914,
2536 + .halt_check = BRANCH_HALT,
2537 + .clkr = {
2538 + .enable_reg = 0x28914,
2539 + .enable_mask = BIT(0),
2540 + .hw.init = &(const struct clk_init_data) {
2541 + .name = "nss_cc_uniphy_port3_rx_clk",
2542 + .parent_data = &(const struct clk_parent_data) {
2543 + .hw = &nss_cc_port3_rx_div_clk_src.clkr.hw,
2544 + },
2545 + .num_parents = 1,
2546 + .flags = CLK_SET_RATE_PARENT,
2547 + .ops = &clk_branch2_ops,
2548 + },
2549 + },
2550 +};
2551 +
2552 +static struct clk_branch nss_cc_uniphy_port3_tx_clk = {
2553 + .halt_reg = 0x28918,
2554 + .halt_check = BRANCH_HALT,
2555 + .clkr = {
2556 + .enable_reg = 0x28918,
2557 + .enable_mask = BIT(0),
2558 + .hw.init = &(const struct clk_init_data) {
2559 + .name = "nss_cc_uniphy_port3_tx_clk",
2560 + .parent_data = &(const struct clk_parent_data) {
2561 + .hw = &nss_cc_port3_tx_div_clk_src.clkr.hw,
2562 + },
2563 + .num_parents = 1,
2564 + .flags = CLK_SET_RATE_PARENT,
2565 + .ops = &clk_branch2_ops,
2566 + },
2567 + },
2568 +};
2569 +
2570 +static struct clk_branch nss_cc_uniphy_port4_rx_clk = {
2571 + .halt_reg = 0x2891c,
2572 + .halt_check = BRANCH_HALT,
2573 + .clkr = {
2574 + .enable_reg = 0x2891c,
2575 + .enable_mask = BIT(0),
2576 + .hw.init = &(const struct clk_init_data) {
2577 + .name = "nss_cc_uniphy_port4_rx_clk",
2578 + .parent_data = &(const struct clk_parent_data) {
2579 + .hw = &nss_cc_port4_rx_div_clk_src.clkr.hw,
2580 + },
2581 + .num_parents = 1,
2582 + .flags = CLK_SET_RATE_PARENT,
2583 + .ops = &clk_branch2_ops,
2584 + },
2585 + },
2586 +};
2587 +
2588 +static struct clk_branch nss_cc_uniphy_port4_tx_clk = {
2589 + .halt_reg = 0x28920,
2590 + .halt_check = BRANCH_HALT,
2591 + .clkr = {
2592 + .enable_reg = 0x28920,
2593 + .enable_mask = BIT(0),
2594 + .hw.init = &(const struct clk_init_data) {
2595 + .name = "nss_cc_uniphy_port4_tx_clk",
2596 + .parent_data = &(const struct clk_parent_data) {
2597 + .hw = &nss_cc_port4_tx_div_clk_src.clkr.hw,
2598 + },
2599 + .num_parents = 1,
2600 + .flags = CLK_SET_RATE_PARENT,
2601 + .ops = &clk_branch2_ops,
2602 + },
2603 + },
2604 +};
2605 +
2606 +static struct clk_branch nss_cc_uniphy_port5_rx_clk = {
2607 + .halt_reg = 0x28924,
2608 + .halt_check = BRANCH_HALT,
2609 + .clkr = {
2610 + .enable_reg = 0x28924,
2611 + .enable_mask = BIT(0),
2612 + .hw.init = &(const struct clk_init_data) {
2613 + .name = "nss_cc_uniphy_port5_rx_clk",
2614 + .parent_data = &(const struct clk_parent_data) {
2615 + .hw = &nss_cc_port5_rx_div_clk_src.clkr.hw,
2616 + },
2617 + .num_parents = 1,
2618 + .flags = CLK_SET_RATE_PARENT,
2619 + .ops = &clk_branch2_ops,
2620 + },
2621 + },
2622 +};
2623 +
2624 +static struct clk_branch nss_cc_uniphy_port5_tx_clk = {
2625 + .halt_reg = 0x28928,
2626 + .halt_check = BRANCH_HALT,
2627 + .clkr = {
2628 + .enable_reg = 0x28928,
2629 + .enable_mask = BIT(0),
2630 + .hw.init = &(const struct clk_init_data) {
2631 + .name = "nss_cc_uniphy_port5_tx_clk",
2632 + .parent_data = &(const struct clk_parent_data) {
2633 + .hw = &nss_cc_port5_tx_div_clk_src.clkr.hw,
2634 + },
2635 + .num_parents = 1,
2636 + .flags = CLK_SET_RATE_PARENT,
2637 + .ops = &clk_branch2_ops,
2638 + },
2639 + },
2640 +};
2641 +
2642 +static struct clk_branch nss_cc_uniphy_port6_rx_clk = {
2643 + .halt_reg = 0x2892c,
2644 + .halt_check = BRANCH_HALT,
2645 + .clkr = {
2646 + .enable_reg = 0x2892c,
2647 + .enable_mask = BIT(0),
2648 + .hw.init = &(const struct clk_init_data) {
2649 + .name = "nss_cc_uniphy_port6_rx_clk",
2650 + .parent_data = &(const struct clk_parent_data) {
2651 + .hw = &nss_cc_port6_rx_div_clk_src.clkr.hw,
2652 + },
2653 + .num_parents = 1,
2654 + .flags = CLK_SET_RATE_PARENT,
2655 + .ops = &clk_branch2_ops,
2656 + },
2657 + },
2658 +};
2659 +
2660 +static struct clk_branch nss_cc_uniphy_port6_tx_clk = {
2661 + .halt_reg = 0x28930,
2662 + .halt_check = BRANCH_HALT,
2663 + .clkr = {
2664 + .enable_reg = 0x28930,
2665 + .enable_mask = BIT(0),
2666 + .hw.init = &(const struct clk_init_data) {
2667 + .name = "nss_cc_uniphy_port6_tx_clk",
2668 + .parent_data = &(const struct clk_parent_data) {
2669 + .hw = &nss_cc_port6_tx_div_clk_src.clkr.hw,
2670 + },
2671 + .num_parents = 1,
2672 + .flags = CLK_SET_RATE_PARENT,
2673 + .ops = &clk_branch2_ops,
2674 + },
2675 + },
2676 +};
2677 +
2678 +static struct clk_branch nss_cc_xgmac0_ptp_ref_clk = {
2679 + .halt_reg = 0x28264,
2680 + .halt_check = BRANCH_HALT,
2681 + .clkr = {
2682 + .enable_reg = 0x28264,
2683 + .enable_mask = BIT(0),
2684 + .hw.init = &(const struct clk_init_data) {
2685 + .name = "nss_cc_xgmac0_ptp_ref_clk",
2686 + .parent_data = &(const struct clk_parent_data) {
2687 + .hw = &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr.hw,
2688 + },
2689 + .num_parents = 1,
2690 + .flags = CLK_SET_RATE_PARENT,
2691 + .ops = &clk_branch2_ops,
2692 + },
2693 + },
2694 +};
2695 +
2696 +static struct clk_branch nss_cc_xgmac1_ptp_ref_clk = {
2697 + .halt_reg = 0x28268,
2698 + .halt_check = BRANCH_HALT,
2699 + .clkr = {
2700 + .enable_reg = 0x28268,
2701 + .enable_mask = BIT(0),
2702 + .hw.init = &(const struct clk_init_data) {
2703 + .name = "nss_cc_xgmac1_ptp_ref_clk",
2704 + .parent_data = &(const struct clk_parent_data) {
2705 + .hw = &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr.hw,
2706 + },
2707 + .num_parents = 1,
2708 + .flags = CLK_SET_RATE_PARENT,
2709 + .ops = &clk_branch2_ops,
2710 + },
2711 + },
2712 +};
2713 +
2714 +static struct clk_branch nss_cc_xgmac2_ptp_ref_clk = {
2715 + .halt_reg = 0x2826c,
2716 + .halt_check = BRANCH_HALT,
2717 + .clkr = {
2718 + .enable_reg = 0x2826c,
2719 + .enable_mask = BIT(0),
2720 + .hw.init = &(const struct clk_init_data) {
2721 + .name = "nss_cc_xgmac2_ptp_ref_clk",
2722 + .parent_data = &(const struct clk_parent_data) {
2723 + .hw = &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr.hw,
2724 + },
2725 + .num_parents = 1,
2726 + .flags = CLK_SET_RATE_PARENT,
2727 + .ops = &clk_branch2_ops,
2728 + },
2729 + },
2730 +};
2731 +
2732 +static struct clk_branch nss_cc_xgmac3_ptp_ref_clk = {
2733 + .halt_reg = 0x28270,
2734 + .halt_check = BRANCH_HALT,
2735 + .clkr = {
2736 + .enable_reg = 0x28270,
2737 + .enable_mask = BIT(0),
2738 + .hw.init = &(const struct clk_init_data) {
2739 + .name = "nss_cc_xgmac3_ptp_ref_clk",
2740 + .parent_data = &(const struct clk_parent_data) {
2741 + .hw = &nss_cc_xgmac3_ptp_ref_div_clk_src.clkr.hw,
2742 + },
2743 + .num_parents = 1,
2744 + .flags = CLK_SET_RATE_PARENT,
2745 + .ops = &clk_branch2_ops,
2746 + },
2747 + },
2748 +};
2749 +
2750 +static struct clk_branch nss_cc_xgmac4_ptp_ref_clk = {
2751 + .halt_reg = 0x28274,
2752 + .halt_check = BRANCH_HALT,
2753 + .clkr = {
2754 + .enable_reg = 0x28274,
2755 + .enable_mask = BIT(0),
2756 + .hw.init = &(const struct clk_init_data) {
2757 + .name = "nss_cc_xgmac4_ptp_ref_clk",
2758 + .parent_data = &(const struct clk_parent_data) {
2759 + .hw = &nss_cc_xgmac4_ptp_ref_div_clk_src.clkr.hw,
2760 + },
2761 + .num_parents = 1,
2762 + .flags = CLK_SET_RATE_PARENT,
2763 + .ops = &clk_branch2_ops,
2764 + },
2765 + },
2766 +};
2767 +
2768 +static struct clk_branch nss_cc_xgmac5_ptp_ref_clk = {
2769 + .halt_reg = 0x28278,
2770 + .halt_check = BRANCH_HALT,
2771 + .clkr = {
2772 + .enable_reg = 0x28278,
2773 + .enable_mask = BIT(0),
2774 + .hw.init = &(const struct clk_init_data) {
2775 + .name = "nss_cc_xgmac5_ptp_ref_clk",
2776 + .parent_data = &(const struct clk_parent_data) {
2777 + .hw = &nss_cc_xgmac5_ptp_ref_div_clk_src.clkr.hw,
2778 + },
2779 + .num_parents = 1,
2780 + .flags = CLK_SET_RATE_PARENT,
2781 + .ops = &clk_branch2_ops,
2782 + },
2783 + },
2784 +};
2785 +
2786 +static struct clk_regmap *nss_cc_ipq9574_clocks[] = {
2787 + [NSS_CC_CE_APB_CLK] = &nss_cc_ce_apb_clk.clkr,
2788 + [NSS_CC_CE_AXI_CLK] = &nss_cc_ce_axi_clk.clkr,
2789 + [NSS_CC_CE_CLK_SRC] = &nss_cc_ce_clk_src.clkr,
2790 + [NSS_CC_CFG_CLK_SRC] = &nss_cc_cfg_clk_src.clkr,
2791 + [NSS_CC_CLC_AXI_CLK] = &nss_cc_clc_axi_clk.clkr,
2792 + [NSS_CC_CLC_CLK_SRC] = &nss_cc_clc_clk_src.clkr,
2793 + [NSS_CC_CRYPTO_CLK] = &nss_cc_crypto_clk.clkr,
2794 + [NSS_CC_CRYPTO_CLK_SRC] = &nss_cc_crypto_clk_src.clkr,
2795 + [NSS_CC_CRYPTO_PPE_CLK] = &nss_cc_crypto_ppe_clk.clkr,
2796 + [NSS_CC_HAQ_AHB_CLK] = &nss_cc_haq_ahb_clk.clkr,
2797 + [NSS_CC_HAQ_AXI_CLK] = &nss_cc_haq_axi_clk.clkr,
2798 + [NSS_CC_HAQ_CLK_SRC] = &nss_cc_haq_clk_src.clkr,
2799 + [NSS_CC_IMEM_AHB_CLK] = &nss_cc_imem_ahb_clk.clkr,
2800 + [NSS_CC_IMEM_CLK_SRC] = &nss_cc_imem_clk_src.clkr,
2801 + [NSS_CC_IMEM_QSB_CLK] = &nss_cc_imem_qsb_clk.clkr,
2802 + [NSS_CC_INT_CFG_CLK_SRC] = &nss_cc_int_cfg_clk_src.clkr,
2803 + [NSS_CC_NSS_CSR_CLK] = &nss_cc_nss_csr_clk.clkr,
2804 + [NSS_CC_NSSNOC_CE_APB_CLK] = &nss_cc_nssnoc_ce_apb_clk.clkr,
2805 + [NSS_CC_NSSNOC_CE_AXI_CLK] = &nss_cc_nssnoc_ce_axi_clk.clkr,
2806 + [NSS_CC_NSSNOC_CLC_AXI_CLK] = &nss_cc_nssnoc_clc_axi_clk.clkr,
2807 + [NSS_CC_NSSNOC_CRYPTO_CLK] = &nss_cc_nssnoc_crypto_clk.clkr,
2808 + [NSS_CC_NSSNOC_HAQ_AHB_CLK] = &nss_cc_nssnoc_haq_ahb_clk.clkr,
2809 + [NSS_CC_NSSNOC_HAQ_AXI_CLK] = &nss_cc_nssnoc_haq_axi_clk.clkr,
2810 + [NSS_CC_NSSNOC_IMEM_AHB_CLK] = &nss_cc_nssnoc_imem_ahb_clk.clkr,
2811 + [NSS_CC_NSSNOC_IMEM_QSB_CLK] = &nss_cc_nssnoc_imem_qsb_clk.clkr,
2812 + [NSS_CC_NSSNOC_NSS_CSR_CLK] = &nss_cc_nssnoc_nss_csr_clk.clkr,
2813 + [NSS_CC_NSSNOC_PPE_CFG_CLK] = &nss_cc_nssnoc_ppe_cfg_clk.clkr,
2814 + [NSS_CC_NSSNOC_PPE_CLK] = &nss_cc_nssnoc_ppe_clk.clkr,
2815 + [NSS_CC_NSSNOC_UBI32_AHB0_CLK] = &nss_cc_nssnoc_ubi32_ahb0_clk.clkr,
2816 + [NSS_CC_NSSNOC_UBI32_AXI0_CLK] = &nss_cc_nssnoc_ubi32_axi0_clk.clkr,
2817 + [NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK] =
2818 + &nss_cc_nssnoc_ubi32_int0_ahb_clk.clkr,
2819 + [NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK] =
2820 + &nss_cc_nssnoc_ubi32_nc_axi0_1_clk.clkr,
2821 + [NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK] =
2822 + &nss_cc_nssnoc_ubi32_nc_axi0_clk.clkr,
2823 + [NSS_CC_PORT1_MAC_CLK] = &nss_cc_port1_mac_clk.clkr,
2824 + [NSS_CC_PORT1_RX_CLK] = &nss_cc_port1_rx_clk.clkr,
2825 + [NSS_CC_PORT1_RX_CLK_SRC] = &nss_cc_port1_rx_clk_src.clkr,
2826 + [NSS_CC_PORT1_RX_DIV_CLK_SRC] = &nss_cc_port1_rx_div_clk_src.clkr,
2827 + [NSS_CC_PORT1_TX_CLK] = &nss_cc_port1_tx_clk.clkr,
2828 + [NSS_CC_PORT1_TX_CLK_SRC] = &nss_cc_port1_tx_clk_src.clkr,
2829 + [NSS_CC_PORT1_TX_DIV_CLK_SRC] = &nss_cc_port1_tx_div_clk_src.clkr,
2830 + [NSS_CC_PORT2_MAC_CLK] = &nss_cc_port2_mac_clk.clkr,
2831 + [NSS_CC_PORT2_RX_CLK] = &nss_cc_port2_rx_clk.clkr,
2832 + [NSS_CC_PORT2_RX_CLK_SRC] = &nss_cc_port2_rx_clk_src.clkr,
2833 + [NSS_CC_PORT2_RX_DIV_CLK_SRC] = &nss_cc_port2_rx_div_clk_src.clkr,
2834 + [NSS_CC_PORT2_TX_CLK] = &nss_cc_port2_tx_clk.clkr,
2835 + [NSS_CC_PORT2_TX_CLK_SRC] = &nss_cc_port2_tx_clk_src.clkr,
2836 + [NSS_CC_PORT2_TX_DIV_CLK_SRC] = &nss_cc_port2_tx_div_clk_src.clkr,
2837 + [NSS_CC_PORT3_MAC_CLK] = &nss_cc_port3_mac_clk.clkr,
2838 + [NSS_CC_PORT3_RX_CLK] = &nss_cc_port3_rx_clk.clkr,
2839 + [NSS_CC_PORT3_RX_CLK_SRC] = &nss_cc_port3_rx_clk_src.clkr,
2840 + [NSS_CC_PORT3_RX_DIV_CLK_SRC] = &nss_cc_port3_rx_div_clk_src.clkr,
2841 + [NSS_CC_PORT3_TX_CLK] = &nss_cc_port3_tx_clk.clkr,
2842 + [NSS_CC_PORT3_TX_CLK_SRC] = &nss_cc_port3_tx_clk_src.clkr,
2843 + [NSS_CC_PORT3_TX_DIV_CLK_SRC] = &nss_cc_port3_tx_div_clk_src.clkr,
2844 + [NSS_CC_PORT4_MAC_CLK] = &nss_cc_port4_mac_clk.clkr,
2845 + [NSS_CC_PORT4_RX_CLK] = &nss_cc_port4_rx_clk.clkr,
2846 + [NSS_CC_PORT4_RX_CLK_SRC] = &nss_cc_port4_rx_clk_src.clkr,
2847 + [NSS_CC_PORT4_RX_DIV_CLK_SRC] = &nss_cc_port4_rx_div_clk_src.clkr,
2848 + [NSS_CC_PORT4_TX_CLK] = &nss_cc_port4_tx_clk.clkr,
2849 + [NSS_CC_PORT4_TX_CLK_SRC] = &nss_cc_port4_tx_clk_src.clkr,
2850 + [NSS_CC_PORT4_TX_DIV_CLK_SRC] = &nss_cc_port4_tx_div_clk_src.clkr,
2851 + [NSS_CC_PORT5_MAC_CLK] = &nss_cc_port5_mac_clk.clkr,
2852 + [NSS_CC_PORT5_RX_CLK] = &nss_cc_port5_rx_clk.clkr,
2853 + [NSS_CC_PORT5_RX_CLK_SRC] = &nss_cc_port5_rx_clk_src.clkr,
2854 + [NSS_CC_PORT5_RX_DIV_CLK_SRC] = &nss_cc_port5_rx_div_clk_src.clkr,
2855 + [NSS_CC_PORT5_TX_CLK] = &nss_cc_port5_tx_clk.clkr,
2856 + [NSS_CC_PORT5_TX_CLK_SRC] = &nss_cc_port5_tx_clk_src.clkr,
2857 + [NSS_CC_PORT5_TX_DIV_CLK_SRC] = &nss_cc_port5_tx_div_clk_src.clkr,
2858 + [NSS_CC_PORT6_MAC_CLK] = &nss_cc_port6_mac_clk.clkr,
2859 + [NSS_CC_PORT6_RX_CLK] = &nss_cc_port6_rx_clk.clkr,
2860 + [NSS_CC_PORT6_RX_CLK_SRC] = &nss_cc_port6_rx_clk_src.clkr,
2861 + [NSS_CC_PORT6_RX_DIV_CLK_SRC] = &nss_cc_port6_rx_div_clk_src.clkr,
2862 + [NSS_CC_PORT6_TX_CLK] = &nss_cc_port6_tx_clk.clkr,
2863 + [NSS_CC_PORT6_TX_CLK_SRC] = &nss_cc_port6_tx_clk_src.clkr,
2864 + [NSS_CC_PORT6_TX_DIV_CLK_SRC] = &nss_cc_port6_tx_div_clk_src.clkr,
2865 + [NSS_CC_PPE_CLK_SRC] = &nss_cc_ppe_clk_src.clkr,
2866 + [NSS_CC_PPE_EDMA_CFG_CLK] = &nss_cc_ppe_edma_cfg_clk.clkr,
2867 + [NSS_CC_PPE_EDMA_CLK] = &nss_cc_ppe_edma_clk.clkr,
2868 + [NSS_CC_PPE_SWITCH_BTQ_CLK] = &nss_cc_ppe_switch_btq_clk.clkr,
2869 + [NSS_CC_PPE_SWITCH_CFG_CLK] = &nss_cc_ppe_switch_cfg_clk.clkr,
2870 + [NSS_CC_PPE_SWITCH_CLK] = &nss_cc_ppe_switch_clk.clkr,
2871 + [NSS_CC_PPE_SWITCH_IPE_CLK] = &nss_cc_ppe_switch_ipe_clk.clkr,
2872 + [NSS_CC_UBI0_CLK_SRC] = &nss_cc_ubi0_clk_src.clkr,
2873 + [NSS_CC_UBI0_DIV_CLK_SRC] = &nss_cc_ubi0_div_clk_src.clkr,
2874 + [NSS_CC_UBI1_CLK_SRC] = &nss_cc_ubi1_clk_src.clkr,
2875 + [NSS_CC_UBI1_DIV_CLK_SRC] = &nss_cc_ubi1_div_clk_src.clkr,
2876 + [NSS_CC_UBI2_CLK_SRC] = &nss_cc_ubi2_clk_src.clkr,
2877 + [NSS_CC_UBI2_DIV_CLK_SRC] = &nss_cc_ubi2_div_clk_src.clkr,
2878 + [NSS_CC_UBI32_AHB0_CLK] = &nss_cc_ubi32_ahb0_clk.clkr,
2879 + [NSS_CC_UBI32_AHB1_CLK] = &nss_cc_ubi32_ahb1_clk.clkr,
2880 + [NSS_CC_UBI32_AHB2_CLK] = &nss_cc_ubi32_ahb2_clk.clkr,
2881 + [NSS_CC_UBI32_AHB3_CLK] = &nss_cc_ubi32_ahb3_clk.clkr,
2882 + [NSS_CC_UBI32_AXI0_CLK] = &nss_cc_ubi32_axi0_clk.clkr,
2883 + [NSS_CC_UBI32_AXI1_CLK] = &nss_cc_ubi32_axi1_clk.clkr,
2884 + [NSS_CC_UBI32_AXI2_CLK] = &nss_cc_ubi32_axi2_clk.clkr,
2885 + [NSS_CC_UBI32_AXI3_CLK] = &nss_cc_ubi32_axi3_clk.clkr,
2886 + [NSS_CC_UBI32_CORE0_CLK] = &nss_cc_ubi32_core0_clk.clkr,
2887 + [NSS_CC_UBI32_CORE1_CLK] = &nss_cc_ubi32_core1_clk.clkr,
2888 + [NSS_CC_UBI32_CORE2_CLK] = &nss_cc_ubi32_core2_clk.clkr,
2889 + [NSS_CC_UBI32_CORE3_CLK] = &nss_cc_ubi32_core3_clk.clkr,
2890 + [NSS_CC_UBI32_INTR0_AHB_CLK] = &nss_cc_ubi32_intr0_ahb_clk.clkr,
2891 + [NSS_CC_UBI32_INTR1_AHB_CLK] = &nss_cc_ubi32_intr1_ahb_clk.clkr,
2892 + [NSS_CC_UBI32_INTR2_AHB_CLK] = &nss_cc_ubi32_intr2_ahb_clk.clkr,
2893 + [NSS_CC_UBI32_INTR3_AHB_CLK] = &nss_cc_ubi32_intr3_ahb_clk.clkr,
2894 + [NSS_CC_UBI32_NC_AXI0_CLK] = &nss_cc_ubi32_nc_axi0_clk.clkr,
2895 + [NSS_CC_UBI32_NC_AXI1_CLK] = &nss_cc_ubi32_nc_axi1_clk.clkr,
2896 + [NSS_CC_UBI32_NC_AXI2_CLK] = &nss_cc_ubi32_nc_axi2_clk.clkr,
2897 + [NSS_CC_UBI32_NC_AXI3_CLK] = &nss_cc_ubi32_nc_axi3_clk.clkr,
2898 + [NSS_CC_UBI32_UTCM0_CLK] = &nss_cc_ubi32_utcm0_clk.clkr,
2899 + [NSS_CC_UBI32_UTCM1_CLK] = &nss_cc_ubi32_utcm1_clk.clkr,
2900 + [NSS_CC_UBI32_UTCM2_CLK] = &nss_cc_ubi32_utcm2_clk.clkr,
2901 + [NSS_CC_UBI32_UTCM3_CLK] = &nss_cc_ubi32_utcm3_clk.clkr,
2902 + [NSS_CC_UBI3_CLK_SRC] = &nss_cc_ubi3_clk_src.clkr,
2903 + [NSS_CC_UBI3_DIV_CLK_SRC] = &nss_cc_ubi3_div_clk_src.clkr,
2904 + [NSS_CC_UBI_AXI_CLK_SRC] = &nss_cc_ubi_axi_clk_src.clkr,
2905 + [NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC] =
2906 + &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr,
2907 + [NSS_CC_UNIPHY_PORT1_RX_CLK] = &nss_cc_uniphy_port1_rx_clk.clkr,
2908 + [NSS_CC_UNIPHY_PORT1_TX_CLK] = &nss_cc_uniphy_port1_tx_clk.clkr,
2909 + [NSS_CC_UNIPHY_PORT2_RX_CLK] = &nss_cc_uniphy_port2_rx_clk.clkr,
2910 + [NSS_CC_UNIPHY_PORT2_TX_CLK] = &nss_cc_uniphy_port2_tx_clk.clkr,
2911 + [NSS_CC_UNIPHY_PORT3_RX_CLK] = &nss_cc_uniphy_port3_rx_clk.clkr,
2912 + [NSS_CC_UNIPHY_PORT3_TX_CLK] = &nss_cc_uniphy_port3_tx_clk.clkr,
2913 + [NSS_CC_UNIPHY_PORT4_RX_CLK] = &nss_cc_uniphy_port4_rx_clk.clkr,
2914 + [NSS_CC_UNIPHY_PORT4_TX_CLK] = &nss_cc_uniphy_port4_tx_clk.clkr,
2915 + [NSS_CC_UNIPHY_PORT5_RX_CLK] = &nss_cc_uniphy_port5_rx_clk.clkr,
2916 + [NSS_CC_UNIPHY_PORT5_TX_CLK] = &nss_cc_uniphy_port5_tx_clk.clkr,
2917 + [NSS_CC_UNIPHY_PORT6_RX_CLK] = &nss_cc_uniphy_port6_rx_clk.clkr,
2918 + [NSS_CC_UNIPHY_PORT6_TX_CLK] = &nss_cc_uniphy_port6_tx_clk.clkr,
2919 + [NSS_CC_XGMAC0_PTP_REF_CLK] = &nss_cc_xgmac0_ptp_ref_clk.clkr,
2920 + [NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC] =
2921 + &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr,
2922 + [NSS_CC_XGMAC1_PTP_REF_CLK] = &nss_cc_xgmac1_ptp_ref_clk.clkr,
2923 + [NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC] =
2924 + &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr,
2925 + [NSS_CC_XGMAC2_PTP_REF_CLK] = &nss_cc_xgmac2_ptp_ref_clk.clkr,
2926 + [NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC] =
2927 + &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr,
2928 + [NSS_CC_XGMAC3_PTP_REF_CLK] = &nss_cc_xgmac3_ptp_ref_clk.clkr,
2929 + [NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC] =
2930 + &nss_cc_xgmac3_ptp_ref_div_clk_src.clkr,
2931 + [NSS_CC_XGMAC4_PTP_REF_CLK] = &nss_cc_xgmac4_ptp_ref_clk.clkr,
2932 + [NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC] =
2933 + &nss_cc_xgmac4_ptp_ref_div_clk_src.clkr,
2934 + [NSS_CC_XGMAC5_PTP_REF_CLK] = &nss_cc_xgmac5_ptp_ref_clk.clkr,
2935 + [NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC] =
2936 + &nss_cc_xgmac5_ptp_ref_div_clk_src.clkr,
2937 + [UBI32_PLL] = &ubi32_pll.clkr,
2938 + [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
2939 +};
2940 +
2941 +static const struct qcom_reset_map nss_cc_ipq9574_resets[] = {
2942 + [NSS_CC_CE_BCR] = { 0x28400, 0 },
2943 + [NSS_CC_CLC_BCR] = { 0x28600, 0 },
2944 + [NSS_CC_EIP197_BCR] = { 0x16004, 0 },
2945 + [NSS_CC_HAQ_BCR] = { 0x28300, 0 },
2946 + [NSS_CC_IMEM_BCR] = { 0xe004, 0 },
2947 + [NSS_CC_MAC_BCR] = { 0x28100, 0 },
2948 + [NSS_CC_PPE_BCR] = { 0x28200, 0 },
2949 + [NSS_CC_UBI_BCR] = { 0x28700, 0 },
2950 + [NSS_CC_UNIPHY_BCR] = { 0x28900, 0 },
2951 + [UBI3_CLKRST_CLAMP_ENABLE] = { 0x28a04, 9 },
2952 + [UBI3_CORE_CLAMP_ENABLE] = { 0x28a04, 8 },
2953 + [UBI2_CLKRST_CLAMP_ENABLE] = { 0x28a04, 7 },
2954 + [UBI2_CORE_CLAMP_ENABLE] = { 0x28a04, 6 },
2955 + [UBI1_CLKRST_CLAMP_ENABLE] = { 0x28a04, 5 },
2956 + [UBI1_CORE_CLAMP_ENABLE] = { 0x28a04, 4 },
2957 + [UBI0_CLKRST_CLAMP_ENABLE] = { 0x28a04, 3 },
2958 + [UBI0_CORE_CLAMP_ENABLE] = { 0x28a04, 2 },
2959 + [NSSNOC_NSS_CSR_ARES] = { 0x28a04, 1 },
2960 + [NSS_CSR_ARES] = { 0x28a04, 0 },
2961 + [PPE_BTQ_ARES] = { 0x28a08, 20 },
2962 + [PPE_IPE_ARES] = { 0x28a08, 19 },
2963 + [PPE_ARES] = { 0x28a08, 18 },
2964 + [PPE_CFG_ARES] = { 0x28a08, 17 },
2965 + [PPE_EDMA_ARES] = { 0x28a08, 16 },
2966 + [PPE_EDMA_CFG_ARES] = { 0x28a08, 15 },
2967 + [CRY_PPE_ARES] = { 0x28a08, 14 },
2968 + [NSSNOC_PPE_ARES] = { 0x28a08, 13 },
2969 + [NSSNOC_PPE_CFG_ARES] = { 0x28a08, 12 },
2970 + [PORT1_MAC_ARES] = { 0x28a08, 11 },
2971 + [PORT2_MAC_ARES] = { 0x28a08, 10 },
2972 + [PORT3_MAC_ARES] = { 0x28a08, 9 },
2973 + [PORT4_MAC_ARES] = { 0x28a08, 8 },
2974 + [PORT5_MAC_ARES] = { 0x28a08, 7 },
2975 + [PORT6_MAC_ARES] = { 0x28a08, 6 },
2976 + [XGMAC0_PTP_REF_ARES] = { 0x28a08, 5 },
2977 + [XGMAC1_PTP_REF_ARES] = { 0x28a08, 4 },
2978 + [XGMAC2_PTP_REF_ARES] = { 0x28a08, 3 },
2979 + [XGMAC3_PTP_REF_ARES] = { 0x28a08, 2 },
2980 + [XGMAC4_PTP_REF_ARES] = { 0x28a08, 1 },
2981 + [XGMAC5_PTP_REF_ARES] = { 0x28a08, 0 },
2982 + [HAQ_AHB_ARES] = { 0x28a0c, 3 },
2983 + [HAQ_AXI_ARES] = { 0x28a0c, 2 },
2984 + [NSSNOC_HAQ_AHB_ARES] = { 0x28a0c, 1 },
2985 + [NSSNOC_HAQ_AXI_ARES] = { 0x28a0c, 0 },
2986 + [CE_APB_ARES] = { 0x28a10, 3 },
2987 + [CE_AXI_ARES] = { 0x28a10, 2 },
2988 + [NSSNOC_CE_APB_ARES] = { 0x28a10, 1 },
2989 + [NSSNOC_CE_AXI_ARES] = { 0x28a10, 0 },
2990 + [CRYPTO_ARES] = { 0x28a14, 1 },
2991 + [NSSNOC_CRYPTO_ARES] = { 0x28a14, 0 },
2992 + [NSSNOC_NC_AXI0_1_ARES] = { 0x28a1c, 28 },
2993 + [UBI0_CORE_ARES] = { 0x28a1c, 27 },
2994 + [UBI1_CORE_ARES] = { 0x28a1c, 26 },
2995 + [UBI2_CORE_ARES] = { 0x28a1c, 25 },
2996 + [UBI3_CORE_ARES] = { 0x28a1c, 24 },
2997 + [NC_AXI0_ARES] = { 0x28a1c, 23 },
2998 + [UTCM0_ARES] = { 0x28a1c, 22 },
2999 + [NC_AXI1_ARES] = { 0x28a1c, 21 },
3000 + [UTCM1_ARES] = { 0x28a1c, 20 },
3001 + [NC_AXI2_ARES] = { 0x28a1c, 19 },
3002 + [UTCM2_ARES] = { 0x28a1c, 18 },
3003 + [NC_AXI3_ARES] = { 0x28a1c, 17 },
3004 + [UTCM3_ARES] = { 0x28a1c, 16 },
3005 + [NSSNOC_NC_AXI0_ARES] = { 0x28a1c, 15 },
3006 + [AHB0_ARES] = { 0x28a1c, 14 },
3007 + [INTR0_AHB_ARES] = { 0x28a1c, 13 },
3008 + [AHB1_ARES] = { 0x28a1c, 12 },
3009 + [INTR1_AHB_ARES] = { 0x28a1c, 11 },
3010 + [AHB2_ARES] = { 0x28a1c, 10 },
3011 + [INTR2_AHB_ARES] = { 0x28a1c, 9 },
3012 + [AHB3_ARES] = { 0x28a1c, 8 },
3013 + [INTR3_AHB_ARES] = { 0x28a1c, 7 },
3014 + [NSSNOC_AHB0_ARES] = { 0x28a1c, 6 },
3015 + [NSSNOC_INT0_AHB_ARES] = { 0x28a1c, 5 },
3016 + [AXI0_ARES] = { 0x28a1c, 4 },
3017 + [AXI1_ARES] = { 0x28a1c, 3 },
3018 + [AXI2_ARES] = { 0x28a1c, 2 },
3019 + [AXI3_ARES] = { 0x28a1c, 1 },
3020 + [NSSNOC_AXI0_ARES] = { 0x28a1c, 0 },
3021 + [IMEM_QSB_ARES] = { 0x28a20, 3 },
3022 + [NSSNOC_IMEM_QSB_ARES] = { 0x28a20, 2 },
3023 + [IMEM_AHB_ARES] = { 0x28a20, 1 },
3024 + [NSSNOC_IMEM_AHB_ARES] = { 0x28a20, 0 },
3025 + [UNIPHY_PORT1_RX_ARES] = { 0x28a24, 23 },
3026 + [UNIPHY_PORT1_TX_ARES] = { 0x28a24, 22 },
3027 + [UNIPHY_PORT2_RX_ARES] = { 0x28a24, 21 },
3028 + [UNIPHY_PORT2_TX_ARES] = { 0x28a24, 20 },
3029 + [UNIPHY_PORT3_RX_ARES] = { 0x28a24, 19 },
3030 + [UNIPHY_PORT3_TX_ARES] = { 0x28a24, 18 },
3031 + [UNIPHY_PORT4_RX_ARES] = { 0x28a24, 17 },
3032 + [UNIPHY_PORT4_TX_ARES] = { 0x28a24, 16 },
3033 + [UNIPHY_PORT5_RX_ARES] = { 0x28a24, 15 },
3034 + [UNIPHY_PORT5_TX_ARES] = { 0x28a24, 14 },
3035 + [UNIPHY_PORT6_RX_ARES] = { 0x28a24, 13 },
3036 + [UNIPHY_PORT6_TX_ARES] = { 0x28a24, 12 },
3037 + [PORT1_RX_ARES] = { 0x28a24, 11 },
3038 + [PORT1_TX_ARES] = { 0x28a24, 10 },
3039 + [PORT2_RX_ARES] = { 0x28a24, 9 },
3040 + [PORT2_TX_ARES] = { 0x28a24, 8 },
3041 + [PORT3_RX_ARES] = { 0x28a24, 7 },
3042 + [PORT3_TX_ARES] = { 0x28a24, 6 },
3043 + [PORT4_RX_ARES] = { 0x28a24, 5 },
3044 + [PORT4_TX_ARES] = { 0x28a24, 4 },
3045 + [PORT5_RX_ARES] = { 0x28a24, 3 },
3046 + [PORT5_TX_ARES] = { 0x28a24, 2 },
3047 + [PORT6_RX_ARES] = { 0x28a24, 1 },
3048 + [PORT6_TX_ARES] = { 0x28a24, 0 },
3049 + [PPE_FULL_RESET] = { .reg = 0x28a08, .bitmask = GENMASK(20, 17) },
3050 + [UNIPHY0_SOFT_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(23, 14) },
3051 + [UNIPHY1_SOFT_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(15, 14) },
3052 + [UNIPHY2_SOFT_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(13, 12) },
3053 + [UNIPHY_PORT1_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(23, 22) },
3054 + [UNIPHY_PORT2_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(21, 20) },
3055 + [UNIPHY_PORT3_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(19, 18) },
3056 + [UNIPHY_PORT4_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(17, 16) },
3057 + [UNIPHY_PORT5_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(15, 14) },
3058 + [UNIPHY_PORT6_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(13, 12) },
3059 + [NSSPORT1_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(11, 10) },
3060 + [NSSPORT2_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(9, 8) },
3061 + [NSSPORT3_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(7, 6) },
3062 + [NSSPORT4_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(5, 4) },
3063 + [NSSPORT5_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(3, 2) },
3064 + [NSSPORT6_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(1, 0) },
3065 + [EDMA_HW_RESET] = { .reg = 0x28a08, .bitmask = GENMASK(16, 15) },
3066 +};
3067 +
3068 +static const struct regmap_config nss_cc_ipq9574_regmap_config = {
3069 + .reg_bits = 32,
3070 + .reg_stride = 4,
3071 + .val_bits = 32,
3072 + .max_register = 0x28a34,
3073 + .fast_io = true,
3074 +};
3075 +
3076 +static struct qcom_icc_hws_data icc_ipq9574_nss_hws[] = {
3077 + { MASTER_NSSNOC_PPE, SLAVE_NSSNOC_PPE, NSS_CC_NSSNOC_PPE_CLK },
3078 + { MASTER_NSSNOC_PPE_CFG, SLAVE_NSSNOC_PPE_CFG, NSS_CC_NSSNOC_PPE_CFG_CLK },
3079 + { MASTER_NSSNOC_NSS_CSR, SLAVE_NSSNOC_NSS_CSR, NSS_CC_NSSNOC_NSS_CSR_CLK },
3080 + { MASTER_NSSNOC_IMEM_QSB, SLAVE_NSSNOC_IMEM_QSB, NSS_CC_NSSNOC_IMEM_QSB_CLK },
3081 + { MASTER_NSSNOC_IMEM_AHB, SLAVE_NSSNOC_IMEM_AHB, NSS_CC_NSSNOC_IMEM_AHB_CLK },
3082 +};
3083 +
3084 +#define IPQ_NSSCC_ID (9574 * 2) /* some unique value */
3085 +
3086 +static const struct qcom_cc_desc nss_cc_ipq9574_desc = {
3087 + .config = &nss_cc_ipq9574_regmap_config,
3088 + .clks = nss_cc_ipq9574_clocks,
3089 + .num_clks = ARRAY_SIZE(nss_cc_ipq9574_clocks),
3090 + .resets = nss_cc_ipq9574_resets,
3091 + .num_resets = ARRAY_SIZE(nss_cc_ipq9574_resets),
3092 + .icc_hws = icc_ipq9574_nss_hws,
3093 + .num_icc_hws = ARRAY_SIZE(icc_ipq9574_nss_hws),
3094 + .icc_first_node_id = IPQ_NSSCC_ID,
3095 +};
3096 +
3097 +static const struct of_device_id nss_cc_ipq9574_match_table[] = {
3098 + { .compatible = "qcom,ipq9574-nsscc" },
3099 + { }
3100 +};
3101 +MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table);
3102 +
3103 +static int nss_cc_ipq9574_probe(struct platform_device *pdev)
3104 +{
3105 + struct regmap *regmap;
3106 +
3107 + regmap = qcom_cc_map(pdev, &nss_cc_ipq9574_desc);
3108 + if (IS_ERR(regmap))
3109 + return PTR_ERR(regmap);
3110 +
3111 + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
3112 +
3113 + return qcom_cc_really_probe(&pdev->dev, &nss_cc_ipq9574_desc, regmap);
3114 +}
3115 +
3116 +static struct platform_driver nss_cc_ipq9574_driver = {
3117 + .probe = nss_cc_ipq9574_probe,
3118 + .driver = {
3119 + .name = "qcom,nsscc-ipq9574",
3120 + .of_match_table = nss_cc_ipq9574_match_table,
3121 + .sync_state = icc_sync_state,
3122 + },
3123 +};
3124 +
3125 +module_platform_driver(nss_cc_ipq9574_driver);
3126 +
3127 +MODULE_DESCRIPTION("QTI NSS_CC IPQ9574 Driver");
3128 +MODULE_LICENSE("GPL");
Mirror of https://github.com/openwrt/openwrt.git