]> git.ipfire.org Git - thirdparty/openwrt.git/blob
projects / thirdparty / openwrt.git / blob
? search:


7161ffe069f37dbf9cc7e66cd8431d86cbe26d82
[thirdparty/openwrt.git] /
1 From e062f073dc0df4fcd338043cb0b69b6bcd31e4af Mon Sep 17 00:00:00 2001
2 From: "SkyLake.Huang" <skylake.huang@mediatek.com>
3 Date: Sat, 9 Nov 2024 00:34:51 +0800
4 Subject: [PATCH 04/20] net: phy: mediatek: Re-organize MediaTek ethernet phy
5 drivers
6
7 Re-organize MediaTek ethernet phy driver files and get ready to integrate
8 some common functions and add new 2.5G phy driver.
9 mtk-ge.c: MT7530 Gphy on MT7621 & MT7531 Gphy
10 mtk-ge-soc.c: Built-in Gphy on MT7981 & Built-in switch Gphy on MT7988
11 mtk-2p5ge.c: Planned for built-in 2.5G phy on MT7988
12
13 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
14 Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
15 Signed-off-by: David S. Miller <davem@davemloft.net>
16 ---
17 MAINTAINERS | 4 ++--
18 drivers/net/phy/Kconfig | 17 +-------------
19 drivers/net/phy/Makefile | 3 +--
20 drivers/net/phy/mediatek/Kconfig | 22 +++++++++++++++++++
21 drivers/net/phy/mediatek/Makefile | 3 +++
22 .../mtk-ge-soc.c} | 0
23 .../phy/{mediatek-ge.c => mediatek/mtk-ge.c} | 0
24 7 files changed, 29 insertions(+), 20 deletions(-)
25 create mode 100644 drivers/net/phy/mediatek/Kconfig
26 create mode 100644 drivers/net/phy/mediatek/Makefile
27 rename drivers/net/phy/{mediatek-ge-soc.c => mediatek/mtk-ge-soc.c} (100%)
28 rename drivers/net/phy/{mediatek-ge.c => mediatek/mtk-ge.c} (100%)
29
30 --- a/MAINTAINERS
31 +++ b/MAINTAINERS
32 @@ -14427,8 +14427,8 @@ M: Qingfang Deng <dqfext@gmail.com>
33 M: SkyLake Huang <SkyLake.Huang@mediatek.com>
34 L: netdev@vger.kernel.org
35 S: Maintained
36 -F: drivers/net/phy/mediatek-ge-soc.c
37 -F: drivers/net/phy/mediatek-ge.c
38 +F: drivers/net/phy/mediatek/mtk-ge-soc.c
39 +F: drivers/net/phy/mediatek/mtk-ge.c
40 F: drivers/phy/mediatek/phy-mtk-xfi-tphy.c
41
42 MEDIATEK I2C CONTROLLER DRIVER
43 --- a/drivers/net/phy/Kconfig
44 +++ b/drivers/net/phy/Kconfig
45 @@ -266,22 +266,7 @@ config MAXLINEAR_GPHY
46 Support for the Maxlinear GPY115, GPY211, GPY212, GPY215,
47 GPY241, GPY245 PHYs.
48
49 -config MEDIATEK_GE_PHY
50 - tristate "MediaTek Gigabit Ethernet PHYs"
51 - help
52 - Supports the MediaTek Gigabit Ethernet PHYs.
53 -
54 -config MEDIATEK_GE_SOC_PHY
55 - tristate "MediaTek SoC Ethernet PHYs"
56 - depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
57 - depends on NVMEM_MTK_EFUSE
58 - help
59 - Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
60 -
61 - Include support for built-in Ethernet PHYs which are present in
62 - the MT7981 and MT7988 SoCs. These PHYs need calibration data
63 - present in the SoCs efuse and will dynamically calibrate VCM
64 - (common-mode voltage) during startup.
65 +source "drivers/net/phy/mediatek/Kconfig"
66
67 config MICREL_PHY
68 tristate "Micrel PHYs"
69 --- a/drivers/net/phy/Makefile
70 +++ b/drivers/net/phy/Makefile
71 @@ -74,8 +74,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o
72 obj-$(CONFIG_MARVELL_88Q2XXX_PHY) += marvell-88q2xxx.o
73 obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
74 obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
75 -obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
76 -obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o
77 +obj-y += mediatek/
78 obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
79 obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
80 obj-$(CONFIG_MICREL_PHY) += micrel.o
81 --- /dev/null
82 +++ b/drivers/net/phy/mediatek/Kconfig
83 @@ -0,0 +1,22 @@
84 +# SPDX-License-Identifier: GPL-2.0-only
85 +config MEDIATEK_GE_PHY
86 + tristate "MediaTek Gigabit Ethernet PHYs"
87 + help
88 + Supports the MediaTek non-built-in Gigabit Ethernet PHYs.
89 +
90 + Non-built-in Gigabit Ethernet PHYs include mt7530/mt7531.
91 + You may find mt7530 inside mt7621. This driver shares some
92 + common operations with MediaTek SoC built-in Gigabit
93 + Ethernet PHYs.
94 +
95 +config MEDIATEK_GE_SOC_PHY
96 + tristate "MediaTek SoC Ethernet PHYs"
97 + depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
98 + depends on NVMEM_MTK_EFUSE
99 + help
100 + Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
101 +
102 + Include support for built-in Ethernet PHYs which are present in
103 + the MT7981 and MT7988 SoCs. These PHYs need calibration data
104 + present in the SoCs efuse and will dynamically calibrate VCM
105 + (common-mode voltage) during startup.
106 --- /dev/null
107 +++ b/drivers/net/phy/mediatek/Makefile
108 @@ -0,0 +1,3 @@
109 +# SPDX-License-Identifier: GPL-2.0
110 +obj-$(CONFIG_MEDIATEK_GE_PHY) += mtk-ge.o
111 +obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mtk-ge-soc.o
112 --- a/drivers/net/phy/mediatek-ge-soc.c
113 +++ /dev/null
114 @@ -1,1610 +0,0 @@
115 -// SPDX-License-Identifier: GPL-2.0+
116 -#include <linux/bitfield.h>
117 -#include <linux/bitmap.h>
118 -#include <linux/mfd/syscon.h>
119 -#include <linux/module.h>
120 -#include <linux/nvmem-consumer.h>
121 -#include <linux/pinctrl/consumer.h>
122 -#include <linux/phy.h>
123 -#include <linux/regmap.h>
124 -
125 -#define MTK_GPHY_ID_MT7981 0x03a29461
126 -#define MTK_GPHY_ID_MT7988 0x03a29481
127 -
128 -#define MTK_EXT_PAGE_ACCESS 0x1f
129 -#define MTK_PHY_PAGE_STANDARD 0x0000
130 -#define MTK_PHY_PAGE_EXTENDED_3 0x0003
131 -
132 -#define MTK_PHY_LPI_REG_14 0x14
133 -#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0)
134 -
135 -#define MTK_PHY_LPI_REG_1c 0x1c
136 -#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
137 -
138 -#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
139 -#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
140 -
141 -#define ANALOG_INTERNAL_OPERATION_MAX_US 20
142 -#define TXRESERVE_MIN 0
143 -#define TXRESERVE_MAX 7
144 -
145 -#define MTK_PHY_ANARG_RG 0x10
146 -#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8)
147 -
148 -/* Registers on MDIO_MMD_VEND1 */
149 -#define MTK_PHY_TXVLD_DA_RG 0x12
150 -#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10)
151 -#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0)
152 -
153 -#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16
154 -#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10)
155 -#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0)
156 -
157 -#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17
158 -#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8)
159 -#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0)
160 -
161 -#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18
162 -#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8)
163 -#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0)
164 -
165 -#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19
166 -#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8)
167 -#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0)
168 -
169 -#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20
170 -#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8)
171 -#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0)
172 -
173 -#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21
174 -#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8)
175 -#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0)
176 -
177 -#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22
178 -#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8)
179 -#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0)
180 -
181 -#define MTK_PHY_RXADC_CTRL_RG7 0xc6
182 -#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
183 -
184 -#define MTK_PHY_RXADC_CTRL_RG9 0xc8
185 -#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12)
186 -#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8)
187 -#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4)
188 -#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
189 -
190 -#define MTK_PHY_LDO_OUTPUT_V 0xd7
191 -
192 -#define MTK_PHY_RG_ANA_CAL_RG0 0xdb
193 -#define MTK_PHY_RG_CAL_CKINV BIT(12)
194 -#define MTK_PHY_RG_ANA_CALEN BIT(8)
195 -#define MTK_PHY_RG_ZCALEN_A BIT(0)
196 -
197 -#define MTK_PHY_RG_ANA_CAL_RG1 0xdc
198 -#define MTK_PHY_RG_ZCALEN_B BIT(12)
199 -#define MTK_PHY_RG_ZCALEN_C BIT(8)
200 -#define MTK_PHY_RG_ZCALEN_D BIT(4)
201 -#define MTK_PHY_RG_TXVOS_CALEN BIT(0)
202 -
203 -#define MTK_PHY_RG_ANA_CAL_RG5 0xe0
204 -#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)
205 -
206 -#define MTK_PHY_RG_TX_FILTER 0xfe
207 -
208 -#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120
209 -#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8)
210 -#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0)
211 -
212 -#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122
213 -#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0)
214 -
215 -#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144
216 -#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5)
217 -
218 -#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172
219 -#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8)
220 -#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)
221 -
222 -#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173
223 -#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8)
224 -#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
225 -
226 -#define MTK_PHY_RG_AD_CAL_COMP 0x17a
227 -#define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8)
228 -
229 -#define MTK_PHY_RG_AD_CAL_CLK 0x17b
230 -#define MTK_PHY_DA_CAL_CLK BIT(0)
231 -
232 -#define MTK_PHY_RG_AD_CALIN 0x17c
233 -#define MTK_PHY_DA_CALIN_FLAG BIT(0)
234 -
235 -#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d
236 -#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0)
237 -
238 -#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e
239 -#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0)
240 -
241 -#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f
242 -#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0)
243 -
244 -#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180
245 -#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0)
246 -
247 -#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181
248 -#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0)
249 -
250 -#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182
251 -#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0)
252 -
253 -#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183
254 -#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0)
255 -
256 -#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184
257 -#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0)
258 -
259 -#define MTK_PHY_RG_DEV1E_REG19b 0x19b
260 -#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8)
261 -
262 -#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a
263 -#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b
264 -#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c
265 -#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d
266 -#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e
267 -#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f
268 -#define MTK_PHY_RG_LP_IIR2_K4_L 0x230
269 -#define MTK_PHY_RG_LP_IIR2_K4_U 0x231
270 -#define MTK_PHY_RG_LP_IIR2_K5_L 0x232
271 -#define MTK_PHY_RG_LP_IIR2_K5_U 0x233
272 -
273 -#define MTK_PHY_RG_DEV1E_REG234 0x234
274 -#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)
275 -#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4)
276 -#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12)
277 -
278 -#define MTK_PHY_RG_LPF_CNT_VAL 0x235
279 -
280 -#define MTK_PHY_RG_DEV1E_REG238 0x238
281 -#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0)
282 -#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12)
283 -
284 -#define MTK_PHY_RG_DEV1E_REG239 0x239
285 -#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0)
286 -#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12)
287 -
288 -#define MTK_PHY_RG_DEV1E_REG27C 0x27c
289 -#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8)
290 -#define MTK_PHY_RG_DEV1E_REG27D 0x27d
291 -#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)
292 -
293 -#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7
294 -#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0)
295 -#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8)
296 -
297 -#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1
298 -#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0)
299 -#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8)
300 -#define MTK_PHY_LPI_TR_READY BIT(9)
301 -#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10)
302 -
303 -#define MTK_PHY_RG_DEV1E_REG323 0x323
304 -#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0)
305 -#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4)
306 -
307 -#define MTK_PHY_RG_DEV1E_REG324 0x324
308 -#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0)
309 -#define MTK_PHY_SMI_DET_MAX_EN BIT(8)
310 -
311 -#define MTK_PHY_RG_DEV1E_REG326 0x326
312 -#define MTK_PHY_LPI_MODE_SD_ON BIT(0)
313 -#define MTK_PHY_RESET_RANDUPD_CNT BIT(1)
314 -#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2)
315 -#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4)
316 -#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5)
317 -
318 -#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502
319 -#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503
320 -
321 -#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d
322 -#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e
323 -#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
324 -#define MTK_PHY_DA_TX_R50_PAIR_D 0x540
325 -
326 -/* Registers on MDIO_MMD_VEND2 */
327 -#define MTK_PHY_LED0_ON_CTRL 0x24
328 -#define MTK_PHY_LED1_ON_CTRL 0x26
329 -#define MTK_PHY_LED_ON_MASK GENMASK(6, 0)
330 -#define MTK_PHY_LED_ON_LINK1000 BIT(0)
331 -#define MTK_PHY_LED_ON_LINK100 BIT(1)
332 -#define MTK_PHY_LED_ON_LINK10 BIT(2)
333 -#define MTK_PHY_LED_ON_LINK (MTK_PHY_LED_ON_LINK10 |\
334 - MTK_PHY_LED_ON_LINK100 |\
335 - MTK_PHY_LED_ON_LINK1000)
336 -#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
337 -#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
338 -#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
339 -#define MTK_PHY_LED_ON_FORCE_ON BIT(6)
340 -#define MTK_PHY_LED_ON_POLARITY BIT(14)
341 -#define MTK_PHY_LED_ON_ENABLE BIT(15)
342 -
343 -#define MTK_PHY_LED0_BLINK_CTRL 0x25
344 -#define MTK_PHY_LED1_BLINK_CTRL 0x27
345 -#define MTK_PHY_LED_BLINK_1000TX BIT(0)
346 -#define MTK_PHY_LED_BLINK_1000RX BIT(1)
347 -#define MTK_PHY_LED_BLINK_100TX BIT(2)
348 -#define MTK_PHY_LED_BLINK_100RX BIT(3)
349 -#define MTK_PHY_LED_BLINK_10TX BIT(4)
350 -#define MTK_PHY_LED_BLINK_10RX BIT(5)
351 -#define MTK_PHY_LED_BLINK_RX (MTK_PHY_LED_BLINK_10RX |\
352 - MTK_PHY_LED_BLINK_100RX |\
353 - MTK_PHY_LED_BLINK_1000RX)
354 -#define MTK_PHY_LED_BLINK_TX (MTK_PHY_LED_BLINK_10TX |\
355 - MTK_PHY_LED_BLINK_100TX |\
356 - MTK_PHY_LED_BLINK_1000TX)
357 -#define MTK_PHY_LED_BLINK_COLLISION BIT(6)
358 -#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
359 -#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
360 -#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9)
361 -
362 -#define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1)
363 -
364 -#define MTK_PHY_RG_BG_RASEL 0x115
365 -#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
366 -
367 -/* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */
368 -#define RG_GPIO_MISC_TPBANK0 0x6f0
369 -#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8)
370 -
371 -/* These macro privides efuse parsing for internal phy. */
372 -#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
373 -#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
374 -#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0))
375 -#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0))
376 -#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0))
377 -
378 -#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0))
379 -#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0))
380 -#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0))
381 -#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0))
382 -#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0))
383 -
384 -#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0))
385 -#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0))
386 -
387 -#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0))
388 -#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0))
389 -
390 -enum {
391 - NO_PAIR,
392 - PAIR_A,
393 - PAIR_B,
394 - PAIR_C,
395 - PAIR_D,
396 -};
397 -
398 -enum calibration_mode {
399 - EFUSE_K,
400 - SW_K
401 -};
402 -
403 -enum CAL_ITEM {
404 - REXT,
405 - TX_OFFSET,
406 - TX_AMP,
407 - TX_R50,
408 - TX_VCM
409 -};
410 -
411 -enum CAL_MODE {
412 - EFUSE_M,
413 - SW_M
414 -};
415 -
416 -#define MTK_PHY_LED_STATE_FORCE_ON 0
417 -#define MTK_PHY_LED_STATE_FORCE_BLINK 1
418 -#define MTK_PHY_LED_STATE_NETDEV 2
419 -
420 -struct mtk_socphy_priv {
421 - unsigned long led_state;
422 -};
423 -
424 -struct mtk_socphy_shared {
425 - u32 boottrap;
426 - struct mtk_socphy_priv priv[4];
427 -};
428 -
429 -static int mtk_socphy_read_page(struct phy_device *phydev)
430 -{
431 - return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
432 -}
433 -
434 -static int mtk_socphy_write_page(struct phy_device *phydev, int page)
435 -{
436 - return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
437 -}
438 -
439 -/* One calibration cycle consists of:
440 - * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
441 - * until AD_CAL_COMP is ready to output calibration result.
442 - * 2.Wait until DA_CAL_CLK is available.
443 - * 3.Fetch AD_CAL_COMP_OUT.
444 - */
445 -static int cal_cycle(struct phy_device *phydev, int devad,
446 - u32 regnum, u16 mask, u16 cal_val)
447 -{
448 - int reg_val;
449 - int ret;
450 -
451 - phy_modify_mmd(phydev, devad, regnum,
452 - mask, cal_val);
453 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
454 - MTK_PHY_DA_CALIN_FLAG);
455 -
456 - ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
457 - MTK_PHY_RG_AD_CAL_CLK, reg_val,
458 - reg_val & MTK_PHY_DA_CAL_CLK, 500,
459 - ANALOG_INTERNAL_OPERATION_MAX_US,
460 - false);
461 - if (ret) {
462 - phydev_err(phydev, "Calibration cycle timeout\n");
463 - return ret;
464 - }
465 -
466 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
467 - MTK_PHY_DA_CALIN_FLAG);
468 - ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP);
469 - if (ret < 0)
470 - return ret;
471 - ret = FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret);
472 - phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
473 -
474 - return ret;
475 -}
476 -
477 -static int rext_fill_result(struct phy_device *phydev, u16 *buf)
478 -{
479 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
480 - MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
481 - phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
482 - MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
483 -
484 - return 0;
485 -}
486 -
487 -static int rext_cal_efuse(struct phy_device *phydev, u32 *buf)
488 -{
489 - u16 rext_cal_val[2];
490 -
491 - rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]);
492 - rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]);
493 - rext_fill_result(phydev, rext_cal_val);
494 -
495 - return 0;
496 -}
497 -
498 -static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
499 -{
500 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
501 - MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8);
502 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
503 - MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]);
504 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
505 - MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8);
506 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
507 - MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]);
508 -
509 - return 0;
510 -}
511 -
512 -static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
513 -{
514 - u16 tx_offset_cal_val[4];
515 -
516 - tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]);
517 - tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]);
518 - tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]);
519 - tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]);
520 -
521 - tx_offset_fill_result(phydev, tx_offset_cal_val);
522 -
523 - return 0;
524 -}
525 -
526 -static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
527 -{
528 - const int vals_9481[16] = { 10, 6, 6, 10,
529 - 10, 6, 6, 10,
530 - 10, 6, 6, 10,
531 - 10, 6, 6, 10 };
532 - const int vals_9461[16] = { 7, 1, 4, 7,
533 - 7, 1, 4, 7,
534 - 7, 1, 4, 7,
535 - 7, 1, 4, 7 };
536 - int bias[16] = {};
537 - int i;
538 -
539 - switch (phydev->drv->phy_id) {
540 - case MTK_GPHY_ID_MT7981:
541 - /* We add some calibration to efuse values
542 - * due to board level influence.
543 - * GBE: +7, TBT: +1, HBT: +4, TST: +7
544 - */
545 - memcpy(bias, (const void *)vals_9461, sizeof(bias));
546 - break;
547 - case MTK_GPHY_ID_MT7988:
548 - memcpy(bias, (const void *)vals_9481, sizeof(bias));
549 - break;
550 - }
551 -
552 - /* Prevent overflow */
553 - for (i = 0; i < 12; i++) {
554 - if (buf[i >> 2] + bias[i] > 63) {
555 - buf[i >> 2] = 63;
556 - bias[i] = 0;
557 - }
558 - }
559 -
560 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
561 - MTK_PHY_DA_TX_I2MPB_A_GBE_MASK,
562 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_GBE_MASK,
563 - buf[0] + bias[0]));
564 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
565 - MTK_PHY_DA_TX_I2MPB_A_TBT_MASK,
566 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TBT_MASK,
567 - buf[0] + bias[1]));
568 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
569 - MTK_PHY_DA_TX_I2MPB_A_HBT_MASK,
570 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_HBT_MASK,
571 - buf[0] + bias[2]));
572 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
573 - MTK_PHY_DA_TX_I2MPB_A_TST_MASK,
574 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TST_MASK,
575 - buf[0] + bias[3]));
576 -
577 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
578 - MTK_PHY_DA_TX_I2MPB_B_GBE_MASK,
579 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_GBE_MASK,
580 - buf[1] + bias[4]));
581 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
582 - MTK_PHY_DA_TX_I2MPB_B_TBT_MASK,
583 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TBT_MASK,
584 - buf[1] + bias[5]));
585 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
586 - MTK_PHY_DA_TX_I2MPB_B_HBT_MASK,
587 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_HBT_MASK,
588 - buf[1] + bias[6]));
589 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
590 - MTK_PHY_DA_TX_I2MPB_B_TST_MASK,
591 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TST_MASK,
592 - buf[1] + bias[7]));
593 -
594 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
595 - MTK_PHY_DA_TX_I2MPB_C_GBE_MASK,
596 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_GBE_MASK,
597 - buf[2] + bias[8]));
598 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
599 - MTK_PHY_DA_TX_I2MPB_C_TBT_MASK,
600 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TBT_MASK,
601 - buf[2] + bias[9]));
602 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
603 - MTK_PHY_DA_TX_I2MPB_C_HBT_MASK,
604 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_HBT_MASK,
605 - buf[2] + bias[10]));
606 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
607 - MTK_PHY_DA_TX_I2MPB_C_TST_MASK,
608 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TST_MASK,
609 - buf[2] + bias[11]));
610 -
611 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
612 - MTK_PHY_DA_TX_I2MPB_D_GBE_MASK,
613 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_GBE_MASK,
614 - buf[3] + bias[12]));
615 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
616 - MTK_PHY_DA_TX_I2MPB_D_TBT_MASK,
617 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TBT_MASK,
618 - buf[3] + bias[13]));
619 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
620 - MTK_PHY_DA_TX_I2MPB_D_HBT_MASK,
621 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_HBT_MASK,
622 - buf[3] + bias[14]));
623 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
624 - MTK_PHY_DA_TX_I2MPB_D_TST_MASK,
625 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TST_MASK,
626 - buf[3] + bias[15]));
627 -
628 - return 0;
629 -}
630 -
631 -static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf)
632 -{
633 - u16 tx_amp_cal_val[4];
634 -
635 - tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]);
636 - tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]);
637 - tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]);
638 - tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]);
639 - tx_amp_fill_result(phydev, tx_amp_cal_val);
640 -
641 - return 0;
642 -}
643 -
644 -static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
645 - u8 txg_calen_x)
646 -{
647 - int bias = 0;
648 - u16 reg, val;
649 -
650 - if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
651 - bias = -1;
652 -
653 - val = clamp_val(bias + tx_r50_cal_val, 0, 63);
654 -
655 - switch (txg_calen_x) {
656 - case PAIR_A:
657 - reg = MTK_PHY_DA_TX_R50_PAIR_A;
658 - break;
659 - case PAIR_B:
660 - reg = MTK_PHY_DA_TX_R50_PAIR_B;
661 - break;
662 - case PAIR_C:
663 - reg = MTK_PHY_DA_TX_R50_PAIR_C;
664 - break;
665 - case PAIR_D:
666 - reg = MTK_PHY_DA_TX_R50_PAIR_D;
667 - break;
668 - default:
669 - return -EINVAL;
670 - }
671 -
672 - phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
673 -
674 - return 0;
675 -}
676 -
677 -static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
678 - u8 txg_calen_x)
679 -{
680 - u16 tx_r50_cal_val;
681 -
682 - switch (txg_calen_x) {
683 - case PAIR_A:
684 - tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]);
685 - break;
686 - case PAIR_B:
687 - tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]);
688 - break;
689 - case PAIR_C:
690 - tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]);
691 - break;
692 - case PAIR_D:
693 - tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]);
694 - break;
695 - default:
696 - return -EINVAL;
697 - }
698 - tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
699 -
700 - return 0;
701 -}
702 -
703 -static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
704 -{
705 - u8 lower_idx, upper_idx, txreserve_val;
706 - u8 lower_ret, upper_ret;
707 - int ret;
708 -
709 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
710 - MTK_PHY_RG_ANA_CALEN);
711 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
712 - MTK_PHY_RG_CAL_CKINV);
713 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
714 - MTK_PHY_RG_TXVOS_CALEN);
715 -
716 - switch (rg_txreserve_x) {
717 - case PAIR_A:
718 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
719 - MTK_PHY_RG_DASN_DAC_IN0_A,
720 - MTK_PHY_DASN_DAC_IN0_A_MASK);
721 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
722 - MTK_PHY_RG_DASN_DAC_IN1_A,
723 - MTK_PHY_DASN_DAC_IN1_A_MASK);
724 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
725 - MTK_PHY_RG_ANA_CAL_RG0,
726 - MTK_PHY_RG_ZCALEN_A);
727 - break;
728 - case PAIR_B:
729 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
730 - MTK_PHY_RG_DASN_DAC_IN0_B,
731 - MTK_PHY_DASN_DAC_IN0_B_MASK);
732 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
733 - MTK_PHY_RG_DASN_DAC_IN1_B,
734 - MTK_PHY_DASN_DAC_IN1_B_MASK);
735 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
736 - MTK_PHY_RG_ANA_CAL_RG1,
737 - MTK_PHY_RG_ZCALEN_B);
738 - break;
739 - case PAIR_C:
740 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
741 - MTK_PHY_RG_DASN_DAC_IN0_C,
742 - MTK_PHY_DASN_DAC_IN0_C_MASK);
743 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
744 - MTK_PHY_RG_DASN_DAC_IN1_C,
745 - MTK_PHY_DASN_DAC_IN1_C_MASK);
746 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
747 - MTK_PHY_RG_ANA_CAL_RG1,
748 - MTK_PHY_RG_ZCALEN_C);
749 - break;
750 - case PAIR_D:
751 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
752 - MTK_PHY_RG_DASN_DAC_IN0_D,
753 - MTK_PHY_DASN_DAC_IN0_D_MASK);
754 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
755 - MTK_PHY_RG_DASN_DAC_IN1_D,
756 - MTK_PHY_DASN_DAC_IN1_D_MASK);
757 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
758 - MTK_PHY_RG_ANA_CAL_RG1,
759 - MTK_PHY_RG_ZCALEN_D);
760 - break;
761 - default:
762 - ret = -EINVAL;
763 - goto restore;
764 - }
765 -
766 - lower_idx = TXRESERVE_MIN;
767 - upper_idx = TXRESERVE_MAX;
768 -
769 - phydev_dbg(phydev, "Start TX-VCM SW cal.\n");
770 - while ((upper_idx - lower_idx) > 1) {
771 - txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2);
772 - ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
773 - MTK_PHY_DA_RX_PSBN_TBT_MASK |
774 - MTK_PHY_DA_RX_PSBN_HBT_MASK |
775 - MTK_PHY_DA_RX_PSBN_GBE_MASK |
776 - MTK_PHY_DA_RX_PSBN_LP_MASK,
777 - txreserve_val << 12 | txreserve_val << 8 |
778 - txreserve_val << 4 | txreserve_val);
779 - if (ret == 1) {
780 - upper_idx = txreserve_val;
781 - upper_ret = ret;
782 - } else if (ret == 0) {
783 - lower_idx = txreserve_val;
784 - lower_ret = ret;
785 - } else {
786 - goto restore;
787 - }
788 - }
789 -
790 - if (lower_idx == TXRESERVE_MIN) {
791 - lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
792 - MTK_PHY_RXADC_CTRL_RG9,
793 - MTK_PHY_DA_RX_PSBN_TBT_MASK |
794 - MTK_PHY_DA_RX_PSBN_HBT_MASK |
795 - MTK_PHY_DA_RX_PSBN_GBE_MASK |
796 - MTK_PHY_DA_RX_PSBN_LP_MASK,
797 - lower_idx << 12 | lower_idx << 8 |
798 - lower_idx << 4 | lower_idx);
799 - ret = lower_ret;
800 - } else if (upper_idx == TXRESERVE_MAX) {
801 - upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
802 - MTK_PHY_RXADC_CTRL_RG9,
803 - MTK_PHY_DA_RX_PSBN_TBT_MASK |
804 - MTK_PHY_DA_RX_PSBN_HBT_MASK |
805 - MTK_PHY_DA_RX_PSBN_GBE_MASK |
806 - MTK_PHY_DA_RX_PSBN_LP_MASK,
807 - upper_idx << 12 | upper_idx << 8 |
808 - upper_idx << 4 | upper_idx);
809 - ret = upper_ret;
810 - }
811 - if (ret < 0)
812 - goto restore;
813 -
814 - /* We calibrate TX-VCM in different logic. Check upper index and then
815 - * lower index. If this calibration is valid, apply lower index's
816 - * result.
817 - */
818 - ret = upper_ret - lower_ret;
819 - if (ret == 1) {
820 - ret = 0;
821 - /* Make sure we use upper_idx in our calibration system */
822 - cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
823 - MTK_PHY_DA_RX_PSBN_TBT_MASK |
824 - MTK_PHY_DA_RX_PSBN_HBT_MASK |
825 - MTK_PHY_DA_RX_PSBN_GBE_MASK |
826 - MTK_PHY_DA_RX_PSBN_LP_MASK,
827 - upper_idx << 12 | upper_idx << 8 |
828 - upper_idx << 4 | upper_idx);
829 - phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
830 - } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
831 - lower_ret == 1) {
832 - ret = 0;
833 - cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
834 - MTK_PHY_DA_RX_PSBN_TBT_MASK |
835 - MTK_PHY_DA_RX_PSBN_HBT_MASK |
836 - MTK_PHY_DA_RX_PSBN_GBE_MASK |
837 - MTK_PHY_DA_RX_PSBN_LP_MASK,
838 - lower_idx << 12 | lower_idx << 8 |
839 - lower_idx << 4 | lower_idx);
840 - phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n",
841 - lower_idx);
842 - } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
843 - lower_ret == 0) {
844 - ret = 0;
845 - phydev_warn(phydev,
846 - "TX-VCM SW cal result at high margin 0x%x\n",
847 - upper_idx);
848 - } else {
849 - ret = -EINVAL;
850 - }
851 -
852 -restore:
853 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
854 - MTK_PHY_RG_ANA_CALEN);
855 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
856 - MTK_PHY_RG_TXVOS_CALEN);
857 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
858 - MTK_PHY_RG_ZCALEN_A);
859 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
860 - MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C |
861 - MTK_PHY_RG_ZCALEN_D);
862 -
863 - return ret;
864 -}
865 -
866 -static void mt798x_phy_common_finetune(struct phy_device *phydev)
867 -{
868 - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
869 - /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
870 - __phy_write(phydev, 0x11, 0xc71);
871 - __phy_write(phydev, 0x12, 0xc);
872 - __phy_write(phydev, 0x10, 0x8fae);
873 -
874 - /* EnabRandUpdTrig = 1 */
875 - __phy_write(phydev, 0x11, 0x2f00);
876 - __phy_write(phydev, 0x12, 0xe);
877 - __phy_write(phydev, 0x10, 0x8fb0);
878 -
879 - /* NormMseLoThresh = 85 */
880 - __phy_write(phydev, 0x11, 0x55a0);
881 - __phy_write(phydev, 0x12, 0x0);
882 - __phy_write(phydev, 0x10, 0x83aa);
883 -
884 - /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
885 - __phy_write(phydev, 0x11, 0x240);
886 - __phy_write(phydev, 0x12, 0x0);
887 - __phy_write(phydev, 0x10, 0x9680);
888 -
889 - /* TrFreeze = 0 (mt7988 default) */
890 - __phy_write(phydev, 0x11, 0x0);
891 - __phy_write(phydev, 0x12, 0x0);
892 - __phy_write(phydev, 0x10, 0x9686);
893 -
894 - /* SSTrKp100 = 5 */
895 - /* SSTrKf100 = 6 */
896 - /* SSTrKp1000Mas = 5 */
897 - /* SSTrKf1000Mas = 6 */
898 - /* SSTrKp1000Slv = 5 */
899 - /* SSTrKf1000Slv = 6 */
900 - __phy_write(phydev, 0x11, 0xbaef);
901 - __phy_write(phydev, 0x12, 0x2e);
902 - __phy_write(phydev, 0x10, 0x968c);
903 - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
904 -}
905 -
906 -static void mt7981_phy_finetune(struct phy_device *phydev)
907 -{
908 - u16 val[8] = { 0x01ce, 0x01c1,
909 - 0x020f, 0x0202,
910 - 0x03d0, 0x03c0,
911 - 0x0013, 0x0005 };
912 - int i, k;
913 -
914 - /* 100M eye finetune:
915 - * Keep middle level of TX MLT3 shapper as default.
916 - * Only change TX MLT3 overshoot level here.
917 - */
918 - for (k = 0, i = 1; i < 12; i++) {
919 - if (i % 3 == 0)
920 - continue;
921 - phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
922 - }
923 -
924 - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
925 - /* ResetSyncOffset = 6 */
926 - __phy_write(phydev, 0x11, 0x600);
927 - __phy_write(phydev, 0x12, 0x0);
928 - __phy_write(phydev, 0x10, 0x8fc0);
929 -
930 - /* VgaDecRate = 1 */
931 - __phy_write(phydev, 0x11, 0x4c2a);
932 - __phy_write(phydev, 0x12, 0x3e);
933 - __phy_write(phydev, 0x10, 0x8fa4);
934 -
935 - /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
936 - * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
937 - */
938 - __phy_write(phydev, 0x11, 0xd10a);
939 - __phy_write(phydev, 0x12, 0x34);
940 - __phy_write(phydev, 0x10, 0x8f82);
941 -
942 - /* VcoSlicerThreshBitsHigh */
943 - __phy_write(phydev, 0x11, 0x5555);
944 - __phy_write(phydev, 0x12, 0x55);
945 - __phy_write(phydev, 0x10, 0x8ec0);
946 - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
947 -
948 - /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
949 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
950 - MTK_PHY_TR_OPEN_LOOP_EN_MASK |
951 - MTK_PHY_LPF_X_AVERAGE_MASK,
952 - BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
953 -
954 - /* rg_tr_lpf_cnt_val = 512 */
955 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
956 -
957 - /* IIR2 related */
958 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
959 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
960 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
961 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
962 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
963 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
964 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
965 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
966 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
967 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
968 -
969 - /* FFE peaking */
970 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
971 - MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
972 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
973 - MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
974 -
975 - /* Disable LDO pump */
976 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
977 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
978 - /* Adjust LDO output voltage */
979 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
980 -}
981 -
982 -static void mt7988_phy_finetune(struct phy_device *phydev)
983 -{
984 - u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
985 - 0x020d, 0x0206, 0x0384, 0x03d0,
986 - 0x03c6, 0x030a, 0x0011, 0x0005 };
987 - int i;
988 -
989 - /* Set default MLT3 shaper first */
990 - for (i = 0; i < 12; i++)
991 - phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
992 -
993 - /* TCT finetune */
994 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
995 -
996 - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
997 - /* ResetSyncOffset = 5 */
998 - __phy_write(phydev, 0x11, 0x500);
999 - __phy_write(phydev, 0x12, 0x0);
1000 - __phy_write(phydev, 0x10, 0x8fc0);
1001 -
1002 - /* VgaDecRate is 1 at default on mt7988 */
1003 -
1004 - /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
1005 - * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
1006 - */
1007 - __phy_write(phydev, 0x11, 0xb90a);
1008 - __phy_write(phydev, 0x12, 0x6f);
1009 - __phy_write(phydev, 0x10, 0x8f82);
1010 -
1011 - /* RemAckCntLimitCtrl = 1 */
1012 - __phy_write(phydev, 0x11, 0xfbba);
1013 - __phy_write(phydev, 0x12, 0xc3);
1014 - __phy_write(phydev, 0x10, 0x87f8);
1015 -
1016 - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
1017 -
1018 - /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
1019 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
1020 - MTK_PHY_TR_OPEN_LOOP_EN_MASK |
1021 - MTK_PHY_LPF_X_AVERAGE_MASK,
1022 - BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
1023 -
1024 - /* rg_tr_lpf_cnt_val = 1023 */
1025 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
1026 -}
1027 -
1028 -static void mt798x_phy_eee(struct phy_device *phydev)
1029 -{
1030 - phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1031 - MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120,
1032 - MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK |
1033 - MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK,
1034 - FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) |
1035 - FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14));
1036 -
1037 - phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1038 - MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
1039 - MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
1040 - FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
1041 - 0xff));
1042 -
1043 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1044 - MTK_PHY_RG_TESTMUX_ADC_CTRL,
1045 - MTK_PHY_RG_TXEN_DIG_MASK);
1046 -
1047 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1048 - MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY);
1049 -
1050 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1051 - MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN);
1052 -
1053 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
1054 - MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK |
1055 - MTK_PHY_LPI_SLV_SEND_TX_EN,
1056 - FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
1057 -
1058 - /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */
1059 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
1060 - MTK_PHY_LPI_TXPCS_LOC_RCV);
1061 -
1062 - /* This also fixes some IoT issues, such as CH340 */
1063 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
1064 - MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
1065 - FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
1066 - FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13));
1067 -
1068 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
1069 - MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
1070 - FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
1071 - 0x33) |
1072 - MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY |
1073 - MTK_PHY_LPI_VCO_EEE_STG0_EN);
1074 -
1075 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
1076 - MTK_PHY_EEE_WAKE_MAS_INT_DC |
1077 - MTK_PHY_EEE_WAKE_SLV_INT_DC);
1078 -
1079 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
1080 - MTK_PHY_SMI_DETCNT_MAX_MASK,
1081 - FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) |
1082 - MTK_PHY_SMI_DET_MAX_EN);
1083 -
1084 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
1085 - MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT |
1086 - MTK_PHY_TREC_UPDATE_ENAB_CLR |
1087 - MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF |
1088 - MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
1089 -
1090 - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
1091 - /* Regsigdet_sel_1000 = 0 */
1092 - __phy_write(phydev, 0x11, 0xb);
1093 - __phy_write(phydev, 0x12, 0x0);
1094 - __phy_write(phydev, 0x10, 0x9690);
1095 -
1096 - /* REG_EEE_st2TrKf1000 = 2 */
1097 - __phy_write(phydev, 0x11, 0x114f);
1098 - __phy_write(phydev, 0x12, 0x2);
1099 - __phy_write(phydev, 0x10, 0x969a);
1100 -
1101 - /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
1102 - __phy_write(phydev, 0x11, 0x3028);
1103 - __phy_write(phydev, 0x12, 0x0);
1104 - __phy_write(phydev, 0x10, 0x969e);
1105 -
1106 - /* RegEEE_slv_wake_int_timer_tar = 8 */
1107 - __phy_write(phydev, 0x11, 0x5010);
1108 - __phy_write(phydev, 0x12, 0x0);
1109 - __phy_write(phydev, 0x10, 0x96a0);
1110 -
1111 - /* RegEEE_trfreeze_timer2 = 586 */
1112 - __phy_write(phydev, 0x11, 0x24a);
1113 - __phy_write(phydev, 0x12, 0x0);
1114 - __phy_write(phydev, 0x10, 0x96a8);
1115 -
1116 - /* RegEEE100Stg1_tar = 16 */
1117 - __phy_write(phydev, 0x11, 0x3210);
1118 - __phy_write(phydev, 0x12, 0x0);
1119 - __phy_write(phydev, 0x10, 0x96b8);
1120 -
1121 - /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
1122 - __phy_write(phydev, 0x11, 0x1463);
1123 - __phy_write(phydev, 0x12, 0x0);
1124 - __phy_write(phydev, 0x10, 0x96ca);
1125 -
1126 - /* DfeTailEnableVgaThresh1000 = 27 */
1127 - __phy_write(phydev, 0x11, 0x36);
1128 - __phy_write(phydev, 0x12, 0x0);
1129 - __phy_write(phydev, 0x10, 0x8f80);
1130 - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
1131 -
1132 - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
1133 - __phy_modify(phydev, MTK_PHY_LPI_REG_14,
1134 - MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
1135 - FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
1136 -
1137 - __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
1138 - FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc));
1139 - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
1140 -
1141 - phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1142 - MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
1143 - MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
1144 - FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
1145 - 0xff));
1146 -}
1147 -
1148 -static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
1149 - u8 start_pair, u8 end_pair)
1150 -{
1151 - u8 pair_n;
1152 - int ret;
1153 -
1154 - for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
1155 - /* TX_OFFSET & TX_AMP have no SW calibration. */
1156 - switch (cal_item) {
1157 - case TX_VCM:
1158 - ret = tx_vcm_cal_sw(phydev, pair_n);
1159 - break;
1160 - default:
1161 - return -EINVAL;
1162 - }
1163 - if (ret)
1164 - return ret;
1165 - }
1166 - return 0;
1167 -}
1168 -
1169 -static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
1170 - u8 start_pair, u8 end_pair, u32 *buf)
1171 -{
1172 - u8 pair_n;
1173 - int ret;
1174 -
1175 - for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
1176 - /* TX_VCM has no efuse calibration. */
1177 - switch (cal_item) {
1178 - case REXT:
1179 - ret = rext_cal_efuse(phydev, buf);
1180 - break;
1181 - case TX_OFFSET:
1182 - ret = tx_offset_cal_efuse(phydev, buf);
1183 - break;
1184 - case TX_AMP:
1185 - ret = tx_amp_cal_efuse(phydev, buf);
1186 - break;
1187 - case TX_R50:
1188 - ret = tx_r50_cal_efuse(phydev, buf, pair_n);
1189 - break;
1190 - default:
1191 - return -EINVAL;
1192 - }
1193 - if (ret)
1194 - return ret;
1195 - }
1196 -
1197 - return 0;
1198 -}
1199 -
1200 -static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
1201 - enum CAL_MODE cal_mode, u8 start_pair,
1202 - u8 end_pair, u32 *buf)
1203 -{
1204 - int ret;
1205 -
1206 - switch (cal_mode) {
1207 - case EFUSE_M:
1208 - ret = cal_efuse(phydev, cal_item, start_pair,
1209 - end_pair, buf);
1210 - break;
1211 - case SW_M:
1212 - ret = cal_sw(phydev, cal_item, start_pair, end_pair);
1213 - break;
1214 - default:
1215 - return -EINVAL;
1216 - }
1217 -
1218 - if (ret) {
1219 - phydev_err(phydev, "cal %d failed\n", cal_item);
1220 - return -EIO;
1221 - }
1222 -
1223 - return 0;
1224 -}
1225 -
1226 -static int mt798x_phy_calibration(struct phy_device *phydev)
1227 -{
1228 - struct nvmem_cell *cell;
1229 - int ret = 0;
1230 - size_t len;
1231 - u32 *buf;
1232 -
1233 - cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
1234 - if (IS_ERR(cell)) {
1235 - if (PTR_ERR(cell) == -EPROBE_DEFER)
1236 - return PTR_ERR(cell);
1237 - return 0;
1238 - }
1239 -
1240 - buf = (u32 *)nvmem_cell_read(cell, &len);
1241 - if (IS_ERR(buf))
1242 - return PTR_ERR(buf);
1243 - nvmem_cell_put(cell);
1244 -
1245 - if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) {
1246 - phydev_err(phydev, "invalid efuse data\n");
1247 - ret = -EINVAL;
1248 - goto out;
1249 - }
1250 -
1251 - ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf);
1252 - if (ret)
1253 - goto out;
1254 - ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf);
1255 - if (ret)
1256 - goto out;
1257 - ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf);
1258 - if (ret)
1259 - goto out;
1260 - ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf);
1261 - if (ret)
1262 - goto out;
1263 - ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf);
1264 - if (ret)
1265 - goto out;
1266 -
1267 -out:
1268 - kfree(buf);
1269 - return ret;
1270 -}
1271 -
1272 -static int mt798x_phy_config_init(struct phy_device *phydev)
1273 -{
1274 - switch (phydev->drv->phy_id) {
1275 - case MTK_GPHY_ID_MT7981:
1276 - mt7981_phy_finetune(phydev);
1277 - break;
1278 - case MTK_GPHY_ID_MT7988:
1279 - mt7988_phy_finetune(phydev);
1280 - break;
1281 - }
1282 -
1283 - mt798x_phy_common_finetune(phydev);
1284 - mt798x_phy_eee(phydev);
1285 -
1286 - return mt798x_phy_calibration(phydev);
1287 -}
1288 -
1289 -static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
1290 - bool on)
1291 -{
1292 - unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
1293 - struct mtk_socphy_priv *priv = phydev->priv;
1294 - bool changed;
1295 -
1296 - if (on)
1297 - changed = !test_and_set_bit(bit_on, &priv->led_state);
1298 - else
1299 - changed = !!test_and_clear_bit(bit_on, &priv->led_state);
1300 -
1301 - changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV +
1302 - (index ? 16 : 0), &priv->led_state);
1303 - if (changed)
1304 - return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
1305 - MTK_PHY_LED1_ON_CTRL :
1306 - MTK_PHY_LED0_ON_CTRL,
1307 - MTK_PHY_LED_ON_MASK,
1308 - on ? MTK_PHY_LED_ON_FORCE_ON : 0);
1309 - else
1310 - return 0;
1311 -}
1312 -
1313 -static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
1314 - bool blinking)
1315 -{
1316 - unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
1317 - (index ? 16 : 0);
1318 - struct mtk_socphy_priv *priv = phydev->priv;
1319 - bool changed;
1320 -
1321 - if (blinking)
1322 - changed = !test_and_set_bit(bit_blink, &priv->led_state);
1323 - else
1324 - changed = !!test_and_clear_bit(bit_blink, &priv->led_state);
1325 -
1326 - changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV +
1327 - (index ? 16 : 0), &priv->led_state);
1328 - if (changed)
1329 - return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
1330 - MTK_PHY_LED1_BLINK_CTRL :
1331 - MTK_PHY_LED0_BLINK_CTRL,
1332 - blinking ?
1333 - MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
1334 - else
1335 - return 0;
1336 -}
1337 -
1338 -static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
1339 - unsigned long *delay_on,
1340 - unsigned long *delay_off)
1341 -{
1342 - bool blinking = false;
1343 - int err = 0;
1344 -
1345 - if (index > 1)
1346 - return -EINVAL;
1347 -
1348 - if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
1349 - blinking = true;
1350 - *delay_on = 50;
1351 - *delay_off = 50;
1352 - }
1353 -
1354 - err = mt798x_phy_hw_led_blink_set(phydev, index, blinking);
1355 - if (err)
1356 - return err;
1357 -
1358 - return mt798x_phy_hw_led_on_set(phydev, index, false);
1359 -}
1360 -
1361 -static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
1362 - u8 index, enum led_brightness value)
1363 -{
1364 - int err;
1365 -
1366 - err = mt798x_phy_hw_led_blink_set(phydev, index, false);
1367 - if (err)
1368 - return err;
1369 -
1370 - return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF));
1371 -}
1372 -
1373 -static const unsigned long supported_triggers =
1374 - BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
1375 - BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
1376 - BIT(TRIGGER_NETDEV_LINK) |
1377 - BIT(TRIGGER_NETDEV_LINK_10) |
1378 - BIT(TRIGGER_NETDEV_LINK_100) |
1379 - BIT(TRIGGER_NETDEV_LINK_1000) |
1380 - BIT(TRIGGER_NETDEV_RX) |
1381 - BIT(TRIGGER_NETDEV_TX);
1382 -
1383 -static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
1384 - unsigned long rules)
1385 -{
1386 - if (index > 1)
1387 - return -EINVAL;
1388 -
1389 - /* All combinations of the supported triggers are allowed */
1390 - if (rules & ~supported_triggers)
1391 - return -EOPNOTSUPP;
1392 -
1393 - return 0;
1394 -};
1395 -
1396 -static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
1397 - unsigned long *rules)
1398 -{
1399 - unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
1400 - (index ? 16 : 0);
1401 - unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
1402 - unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
1403 - struct mtk_socphy_priv *priv = phydev->priv;
1404 - int on, blink;
1405 -
1406 - if (index > 1)
1407 - return -EINVAL;
1408 -
1409 - on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1410 - index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL);
1411 -
1412 - if (on < 0)
1413 - return -EIO;
1414 -
1415 - blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1416 - index ? MTK_PHY_LED1_BLINK_CTRL :
1417 - MTK_PHY_LED0_BLINK_CTRL);
1418 - if (blink < 0)
1419 - return -EIO;
1420 -
1421 - if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX |
1422 - MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) ||
1423 - (blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX)))
1424 - set_bit(bit_netdev, &priv->led_state);
1425 - else
1426 - clear_bit(bit_netdev, &priv->led_state);
1427 -
1428 - if (on & MTK_PHY_LED_ON_FORCE_ON)
1429 - set_bit(bit_on, &priv->led_state);
1430 - else
1431 - clear_bit(bit_on, &priv->led_state);
1432 -
1433 - if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK)
1434 - set_bit(bit_blink, &priv->led_state);
1435 - else
1436 - clear_bit(bit_blink, &priv->led_state);
1437 -
1438 - if (!rules)
1439 - return 0;
1440 -
1441 - if (on & MTK_PHY_LED_ON_LINK)
1442 - *rules |= BIT(TRIGGER_NETDEV_LINK);
1443 -
1444 - if (on & MTK_PHY_LED_ON_LINK10)
1445 - *rules |= BIT(TRIGGER_NETDEV_LINK_10);
1446 -
1447 - if (on & MTK_PHY_LED_ON_LINK100)
1448 - *rules |= BIT(TRIGGER_NETDEV_LINK_100);
1449 -
1450 - if (on & MTK_PHY_LED_ON_LINK1000)
1451 - *rules |= BIT(TRIGGER_NETDEV_LINK_1000);
1452 -
1453 - if (on & MTK_PHY_LED_ON_FDX)
1454 - *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
1455 -
1456 - if (on & MTK_PHY_LED_ON_HDX)
1457 - *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
1458 -
1459 - if (blink & MTK_PHY_LED_BLINK_RX)
1460 - *rules |= BIT(TRIGGER_NETDEV_RX);
1461 -
1462 - if (blink & MTK_PHY_LED_BLINK_TX)
1463 - *rules |= BIT(TRIGGER_NETDEV_TX);
1464 -
1465 - return 0;
1466 -};
1467 -
1468 -static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
1469 - unsigned long rules)
1470 -{
1471 - unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
1472 - struct mtk_socphy_priv *priv = phydev->priv;
1473 - u16 on = 0, blink = 0;
1474 - int ret;
1475 -
1476 - if (index > 1)
1477 - return -EINVAL;
1478 -
1479 - if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
1480 - on |= MTK_PHY_LED_ON_FDX;
1481 -
1482 - if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
1483 - on |= MTK_PHY_LED_ON_HDX;
1484 -
1485 - if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
1486 - on |= MTK_PHY_LED_ON_LINK10;
1487 -
1488 - if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
1489 - on |= MTK_PHY_LED_ON_LINK100;
1490 -
1491 - if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
1492 - on |= MTK_PHY_LED_ON_LINK1000;
1493 -
1494 - if (rules & BIT(TRIGGER_NETDEV_RX)) {
1495 - blink |= (on & MTK_PHY_LED_ON_LINK) ?
1496 - (((on & MTK_PHY_LED_ON_LINK10) ?
1497 - MTK_PHY_LED_BLINK_10RX : 0) |
1498 - ((on & MTK_PHY_LED_ON_LINK100) ?
1499 - MTK_PHY_LED_BLINK_100RX : 0) |
1500 - ((on & MTK_PHY_LED_ON_LINK1000) ?
1501 - MTK_PHY_LED_BLINK_1000RX : 0)) :
1502 - MTK_PHY_LED_BLINK_RX;
1503 - }
1504 -
1505 - if (rules & BIT(TRIGGER_NETDEV_TX)) {
1506 - blink |= (on & MTK_PHY_LED_ON_LINK) ?
1507 - (((on & MTK_PHY_LED_ON_LINK10) ?
1508 - MTK_PHY_LED_BLINK_10TX : 0) |
1509 - ((on & MTK_PHY_LED_ON_LINK100) ?
1510 - MTK_PHY_LED_BLINK_100TX : 0) |
1511 - ((on & MTK_PHY_LED_ON_LINK1000) ?
1512 - MTK_PHY_LED_BLINK_1000TX : 0)) :
1513 - MTK_PHY_LED_BLINK_TX;
1514 - }
1515 -
1516 - if (blink || on)
1517 - set_bit(bit_netdev, &priv->led_state);
1518 - else
1519 - clear_bit(bit_netdev, &priv->led_state);
1520 -
1521 - ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
1522 - MTK_PHY_LED1_ON_CTRL :
1523 - MTK_PHY_LED0_ON_CTRL,
1524 - MTK_PHY_LED_ON_FDX |
1525 - MTK_PHY_LED_ON_HDX |
1526 - MTK_PHY_LED_ON_LINK,
1527 - on);
1528 -
1529 - if (ret)
1530 - return ret;
1531 -
1532 - return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
1533 - MTK_PHY_LED1_BLINK_CTRL :
1534 - MTK_PHY_LED0_BLINK_CTRL, blink);
1535 -};
1536 -
1537 -static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num)
1538 -{
1539 - struct mtk_socphy_shared *priv = phydev->shared->priv;
1540 - u32 polarities;
1541 -
1542 - if (led_num == 0)
1543 - polarities = ~(priv->boottrap);
1544 - else
1545 - polarities = MTK_PHY_LED1_DEFAULT_POLARITIES;
1546 -
1547 - if (polarities & BIT(phydev->mdio.addr))
1548 - return true;
1549 -
1550 - return false;
1551 -}
1552 -
1553 -static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev)
1554 -{
1555 - struct pinctrl *pinctrl;
1556 - int index;
1557 -
1558 - /* Setup LED polarity according to bootstrap use of LED pins */
1559 - for (index = 0; index < 2; ++index)
1560 - phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
1561 - MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
1562 - MTK_PHY_LED_ON_POLARITY,
1563 - mt7988_phy_led_get_polarity(phydev, index) ?
1564 - MTK_PHY_LED_ON_POLARITY : 0);
1565 -
1566 - /* Only now setup pinctrl to avoid bogus blinking */
1567 - pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
1568 - if (IS_ERR(pinctrl))
1569 - dev_err(&phydev->mdio.bus->dev,
1570 - "Failed to setup PHY LED pinctrl\n");
1571 -
1572 - return 0;
1573 -}
1574 -
1575 -static int mt7988_phy_probe_shared(struct phy_device *phydev)
1576 -{
1577 - struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
1578 - struct mtk_socphy_shared *shared = phydev->shared->priv;
1579 - struct regmap *regmap;
1580 - u32 reg;
1581 - int ret;
1582 -
1583 - /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B,
1584 - * LED_C and LED_D respectively. At the same time those pins are used to
1585 - * bootstrap configuration of the reference clock source (LED_A),
1586 - * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
1587 - * In practice this is done using a LED and a resistor pulling the pin
1588 - * either to GND or to VIO.
1589 - * The detected value at boot time is accessible at run-time using the
1590 - * TPBANK0 register located in the gpio base of the pinctrl, in order
1591 - * to read it here it needs to be referenced by a phandle called
1592 - * 'mediatek,pio' in the MDIO bus hosting the PHY.
1593 - * The 4 bits in TPBANK0 are kept as package shared data and are used to
1594 - * set LED polarity for each of the LED0.
1595 - */
1596 - regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio");
1597 - if (IS_ERR(regmap))
1598 - return PTR_ERR(regmap);
1599 -
1600 - ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, &reg);
1601 - if (ret)
1602 - return ret;
1603 -
1604 - shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg);
1605 -
1606 - return 0;
1607 -}
1608 -
1609 -static void mt798x_phy_leds_state_init(struct phy_device *phydev)
1610 -{
1611 - int i;
1612 -
1613 - for (i = 0; i < 2; ++i)
1614 - mt798x_phy_led_hw_control_get(phydev, i, NULL);
1615 -}
1616 -
1617 -static int mt7988_phy_probe(struct phy_device *phydev)
1618 -{
1619 - struct mtk_socphy_shared *shared;
1620 - struct mtk_socphy_priv *priv;
1621 - int err;
1622 -
1623 - if (phydev->mdio.addr > 3)
1624 - return -EINVAL;
1625 -
1626 - err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
1627 - sizeof(struct mtk_socphy_shared));
1628 - if (err)
1629 - return err;
1630 -
1631 - if (phy_package_probe_once(phydev)) {
1632 - err = mt7988_phy_probe_shared(phydev);
1633 - if (err)
1634 - return err;
1635 - }
1636 -
1637 - shared = phydev->shared->priv;
1638 - priv = &shared->priv[phydev->mdio.addr];
1639 -
1640 - phydev->priv = priv;
1641 -
1642 - mt798x_phy_leds_state_init(phydev);
1643 -
1644 - err = mt7988_phy_fix_leds_polarities(phydev);
1645 - if (err)
1646 - return err;
1647 -
1648 - /* Disable TX power saving at probing to:
1649 - * 1. Meet common mode compliance test criteria
1650 - * 2. Make sure that TX-VCM calibration works fine
1651 - */
1652 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
1653 - MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
1654 -
1655 - return mt798x_phy_calibration(phydev);
1656 -}
1657 -
1658 -static int mt7981_phy_probe(struct phy_device *phydev)
1659 -{
1660 - struct mtk_socphy_priv *priv;
1661 -
1662 - priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv),
1663 - GFP_KERNEL);
1664 - if (!priv)
1665 - return -ENOMEM;
1666 -
1667 - phydev->priv = priv;
1668 -
1669 - mt798x_phy_leds_state_init(phydev);
1670 -
1671 - return mt798x_phy_calibration(phydev);
1672 -}
1673 -
1674 -static struct phy_driver mtk_socphy_driver[] = {
1675 - {
1676 - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
1677 - .name = "MediaTek MT7981 PHY",
1678 - .config_init = mt798x_phy_config_init,
1679 - .config_intr = genphy_no_config_intr,
1680 - .handle_interrupt = genphy_handle_interrupt_no_ack,
1681 - .probe = mt7981_phy_probe,
1682 - .suspend = genphy_suspend,
1683 - .resume = genphy_resume,
1684 - .read_page = mtk_socphy_read_page,
1685 - .write_page = mtk_socphy_write_page,
1686 - .led_blink_set = mt798x_phy_led_blink_set,
1687 - .led_brightness_set = mt798x_phy_led_brightness_set,
1688 - .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
1689 - .led_hw_control_set = mt798x_phy_led_hw_control_set,
1690 - .led_hw_control_get = mt798x_phy_led_hw_control_get,
1691 - },
1692 - {
1693 - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
1694 - .name = "MediaTek MT7988 PHY",
1695 - .config_init = mt798x_phy_config_init,
1696 - .config_intr = genphy_no_config_intr,
1697 - .handle_interrupt = genphy_handle_interrupt_no_ack,
1698 - .probe = mt7988_phy_probe,
1699 - .suspend = genphy_suspend,
1700 - .resume = genphy_resume,
1701 - .read_page = mtk_socphy_read_page,
1702 - .write_page = mtk_socphy_write_page,
1703 - .led_blink_set = mt798x_phy_led_blink_set,
1704 - .led_brightness_set = mt798x_phy_led_brightness_set,
1705 - .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
1706 - .led_hw_control_set = mt798x_phy_led_hw_control_set,
1707 - .led_hw_control_get = mt798x_phy_led_hw_control_get,
1708 - },
1709 -};
1710 -
1711 -module_phy_driver(mtk_socphy_driver);
1712 -
1713 -static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
1714 - { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
1715 - { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
1716 - { }
1717 -};
1718 -
1719 -MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver");
1720 -MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
1721 -MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
1722 -MODULE_LICENSE("GPL");
1723 -
1724 -MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl);
1725 --- a/drivers/net/phy/mediatek-ge.c
1726 +++ /dev/null
1727 @@ -1,111 +0,0 @@
1728 -// SPDX-License-Identifier: GPL-2.0+
1729 -#include <linux/bitfield.h>
1730 -#include <linux/module.h>
1731 -#include <linux/phy.h>
1732 -
1733 -#define MTK_EXT_PAGE_ACCESS 0x1f
1734 -#define MTK_PHY_PAGE_STANDARD 0x0000
1735 -#define MTK_PHY_PAGE_EXTENDED 0x0001
1736 -#define MTK_PHY_PAGE_EXTENDED_2 0x0002
1737 -#define MTK_PHY_PAGE_EXTENDED_3 0x0003
1738 -#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
1739 -#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
1740 -
1741 -static int mtk_gephy_read_page(struct phy_device *phydev)
1742 -{
1743 - return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
1744 -}
1745 -
1746 -static int mtk_gephy_write_page(struct phy_device *phydev, int page)
1747 -{
1748 - return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
1749 -}
1750 -
1751 -static void mtk_gephy_config_init(struct phy_device *phydev)
1752 -{
1753 - /* Enable HW auto downshift */
1754 - phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
1755 -
1756 - /* Increase SlvDPSready time */
1757 - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
1758 - __phy_write(phydev, 0x10, 0xafae);
1759 - __phy_write(phydev, 0x12, 0x2f);
1760 - __phy_write(phydev, 0x10, 0x8fae);
1761 - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
1762 -
1763 - /* Adjust 100_mse_threshold */
1764 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
1765 -
1766 - /* Disable mcc */
1767 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
1768 -}
1769 -
1770 -static int mt7530_phy_config_init(struct phy_device *phydev)
1771 -{
1772 - mtk_gephy_config_init(phydev);
1773 -
1774 - /* Increase post_update_timer */
1775 - phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
1776 -
1777 - return 0;
1778 -}
1779 -
1780 -static int mt7531_phy_config_init(struct phy_device *phydev)
1781 -{
1782 - mtk_gephy_config_init(phydev);
1783 -
1784 - /* PHY link down power saving enable */
1785 - phy_set_bits(phydev, 0x17, BIT(4));
1786 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
1787 -
1788 - /* Set TX Pair delay selection */
1789 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
1790 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
1791 -
1792 - return 0;
1793 -}
1794 -
1795 -static struct phy_driver mtk_gephy_driver[] = {
1796 - {
1797 - PHY_ID_MATCH_EXACT(0x03a29412),
1798 - .name = "MediaTek MT7530 PHY",
1799 - .config_init = mt7530_phy_config_init,
1800 - /* Interrupts are handled by the switch, not the PHY
1801 - * itself.
1802 - */
1803 - .config_intr = genphy_no_config_intr,
1804 - .handle_interrupt = genphy_handle_interrupt_no_ack,
1805 - .suspend = genphy_suspend,
1806 - .resume = genphy_resume,
1807 - .read_page = mtk_gephy_read_page,
1808 - .write_page = mtk_gephy_write_page,
1809 - },
1810 - {
1811 - PHY_ID_MATCH_EXACT(0x03a29441),
1812 - .name = "MediaTek MT7531 PHY",
1813 - .config_init = mt7531_phy_config_init,
1814 - /* Interrupts are handled by the switch, not the PHY
1815 - * itself.
1816 - */
1817 - .config_intr = genphy_no_config_intr,
1818 - .handle_interrupt = genphy_handle_interrupt_no_ack,
1819 - .suspend = genphy_suspend,
1820 - .resume = genphy_resume,
1821 - .read_page = mtk_gephy_read_page,
1822 - .write_page = mtk_gephy_write_page,
1823 - },
1824 -};
1825 -
1826 -module_phy_driver(mtk_gephy_driver);
1827 -
1828 -static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
1829 - { PHY_ID_MATCH_EXACT(0x03a29441) },
1830 - { PHY_ID_MATCH_EXACT(0x03a29412) },
1831 - { }
1832 -};
1833 -
1834 -MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver");
1835 -MODULE_AUTHOR("DENG, Qingfang <dqfext@gmail.com>");
1836 -MODULE_LICENSE("GPL");
1837 -
1838 -MODULE_DEVICE_TABLE(mdio, mtk_gephy_tbl);
1839 --- /dev/null
1840 +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
1841 @@ -0,0 +1,1610 @@
1842 +// SPDX-License-Identifier: GPL-2.0+
1843 +#include <linux/bitfield.h>
1844 +#include <linux/bitmap.h>
1845 +#include <linux/mfd/syscon.h>
1846 +#include <linux/module.h>
1847 +#include <linux/nvmem-consumer.h>
1848 +#include <linux/pinctrl/consumer.h>
1849 +#include <linux/phy.h>
1850 +#include <linux/regmap.h>
1851 +
1852 +#define MTK_GPHY_ID_MT7981 0x03a29461
1853 +#define MTK_GPHY_ID_MT7988 0x03a29481
1854 +
1855 +#define MTK_EXT_PAGE_ACCESS 0x1f
1856 +#define MTK_PHY_PAGE_STANDARD 0x0000
1857 +#define MTK_PHY_PAGE_EXTENDED_3 0x0003
1858 +
1859 +#define MTK_PHY_LPI_REG_14 0x14
1860 +#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0)
1861 +
1862 +#define MTK_PHY_LPI_REG_1c 0x1c
1863 +#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
1864 +
1865 +#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
1866 +#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
1867 +
1868 +#define ANALOG_INTERNAL_OPERATION_MAX_US 20
1869 +#define TXRESERVE_MIN 0
1870 +#define TXRESERVE_MAX 7
1871 +
1872 +#define MTK_PHY_ANARG_RG 0x10
1873 +#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8)
1874 +
1875 +/* Registers on MDIO_MMD_VEND1 */
1876 +#define MTK_PHY_TXVLD_DA_RG 0x12
1877 +#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10)
1878 +#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0)
1879 +
1880 +#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16
1881 +#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10)
1882 +#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0)
1883 +
1884 +#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17
1885 +#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8)
1886 +#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0)
1887 +
1888 +#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18
1889 +#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8)
1890 +#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0)
1891 +
1892 +#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19
1893 +#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8)
1894 +#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0)
1895 +
1896 +#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20
1897 +#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8)
1898 +#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0)
1899 +
1900 +#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21
1901 +#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8)
1902 +#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0)
1903 +
1904 +#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22
1905 +#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8)
1906 +#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0)
1907 +
1908 +#define MTK_PHY_RXADC_CTRL_RG7 0xc6
1909 +#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
1910 +
1911 +#define MTK_PHY_RXADC_CTRL_RG9 0xc8
1912 +#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12)
1913 +#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8)
1914 +#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4)
1915 +#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
1916 +
1917 +#define MTK_PHY_LDO_OUTPUT_V 0xd7
1918 +
1919 +#define MTK_PHY_RG_ANA_CAL_RG0 0xdb
1920 +#define MTK_PHY_RG_CAL_CKINV BIT(12)
1921 +#define MTK_PHY_RG_ANA_CALEN BIT(8)
1922 +#define MTK_PHY_RG_ZCALEN_A BIT(0)
1923 +
1924 +#define MTK_PHY_RG_ANA_CAL_RG1 0xdc
1925 +#define MTK_PHY_RG_ZCALEN_B BIT(12)
1926 +#define MTK_PHY_RG_ZCALEN_C BIT(8)
1927 +#define MTK_PHY_RG_ZCALEN_D BIT(4)
1928 +#define MTK_PHY_RG_TXVOS_CALEN BIT(0)
1929 +
1930 +#define MTK_PHY_RG_ANA_CAL_RG5 0xe0
1931 +#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)
1932 +
1933 +#define MTK_PHY_RG_TX_FILTER 0xfe
1934 +
1935 +#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120
1936 +#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8)
1937 +#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0)
1938 +
1939 +#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122
1940 +#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0)
1941 +
1942 +#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144
1943 +#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5)
1944 +
1945 +#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172
1946 +#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8)
1947 +#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)
1948 +
1949 +#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173
1950 +#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8)
1951 +#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
1952 +
1953 +#define MTK_PHY_RG_AD_CAL_COMP 0x17a
1954 +#define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8)
1955 +
1956 +#define MTK_PHY_RG_AD_CAL_CLK 0x17b
1957 +#define MTK_PHY_DA_CAL_CLK BIT(0)
1958 +
1959 +#define MTK_PHY_RG_AD_CALIN 0x17c
1960 +#define MTK_PHY_DA_CALIN_FLAG BIT(0)
1961 +
1962 +#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d
1963 +#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0)
1964 +
1965 +#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e
1966 +#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0)
1967 +
1968 +#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f
1969 +#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0)
1970 +
1971 +#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180
1972 +#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0)
1973 +
1974 +#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181
1975 +#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0)
1976 +
1977 +#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182
1978 +#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0)
1979 +
1980 +#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183
1981 +#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0)
1982 +
1983 +#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184
1984 +#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0)
1985 +
1986 +#define MTK_PHY_RG_DEV1E_REG19b 0x19b
1987 +#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8)
1988 +
1989 +#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a
1990 +#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b
1991 +#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c
1992 +#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d
1993 +#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e
1994 +#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f
1995 +#define MTK_PHY_RG_LP_IIR2_K4_L 0x230
1996 +#define MTK_PHY_RG_LP_IIR2_K4_U 0x231
1997 +#define MTK_PHY_RG_LP_IIR2_K5_L 0x232
1998 +#define MTK_PHY_RG_LP_IIR2_K5_U 0x233
1999 +
2000 +#define MTK_PHY_RG_DEV1E_REG234 0x234
2001 +#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)
2002 +#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4)
2003 +#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12)
2004 +
2005 +#define MTK_PHY_RG_LPF_CNT_VAL 0x235
2006 +
2007 +#define MTK_PHY_RG_DEV1E_REG238 0x238
2008 +#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0)
2009 +#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12)
2010 +
2011 +#define MTK_PHY_RG_DEV1E_REG239 0x239
2012 +#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0)
2013 +#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12)
2014 +
2015 +#define MTK_PHY_RG_DEV1E_REG27C 0x27c
2016 +#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8)
2017 +#define MTK_PHY_RG_DEV1E_REG27D 0x27d
2018 +#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)
2019 +
2020 +#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7
2021 +#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0)
2022 +#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8)
2023 +
2024 +#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1
2025 +#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0)
2026 +#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8)
2027 +#define MTK_PHY_LPI_TR_READY BIT(9)
2028 +#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10)
2029 +
2030 +#define MTK_PHY_RG_DEV1E_REG323 0x323
2031 +#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0)
2032 +#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4)
2033 +
2034 +#define MTK_PHY_RG_DEV1E_REG324 0x324
2035 +#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0)
2036 +#define MTK_PHY_SMI_DET_MAX_EN BIT(8)
2037 +
2038 +#define MTK_PHY_RG_DEV1E_REG326 0x326
2039 +#define MTK_PHY_LPI_MODE_SD_ON BIT(0)
2040 +#define MTK_PHY_RESET_RANDUPD_CNT BIT(1)
2041 +#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2)
2042 +#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4)
2043 +#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5)
2044 +
2045 +#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502
2046 +#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503
2047 +
2048 +#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d
2049 +#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e
2050 +#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
2051 +#define MTK_PHY_DA_TX_R50_PAIR_D 0x540
2052 +
2053 +/* Registers on MDIO_MMD_VEND2 */
2054 +#define MTK_PHY_LED0_ON_CTRL 0x24
2055 +#define MTK_PHY_LED1_ON_CTRL 0x26
2056 +#define MTK_PHY_LED_ON_MASK GENMASK(6, 0)
2057 +#define MTK_PHY_LED_ON_LINK1000 BIT(0)
2058 +#define MTK_PHY_LED_ON_LINK100 BIT(1)
2059 +#define MTK_PHY_LED_ON_LINK10 BIT(2)
2060 +#define MTK_PHY_LED_ON_LINK (MTK_PHY_LED_ON_LINK10 |\
2061 + MTK_PHY_LED_ON_LINK100 |\
2062 + MTK_PHY_LED_ON_LINK1000)
2063 +#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
2064 +#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
2065 +#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
2066 +#define MTK_PHY_LED_ON_FORCE_ON BIT(6)
2067 +#define MTK_PHY_LED_ON_POLARITY BIT(14)
2068 +#define MTK_PHY_LED_ON_ENABLE BIT(15)
2069 +
2070 +#define MTK_PHY_LED0_BLINK_CTRL 0x25
2071 +#define MTK_PHY_LED1_BLINK_CTRL 0x27
2072 +#define MTK_PHY_LED_BLINK_1000TX BIT(0)
2073 +#define MTK_PHY_LED_BLINK_1000RX BIT(1)
2074 +#define MTK_PHY_LED_BLINK_100TX BIT(2)
2075 +#define MTK_PHY_LED_BLINK_100RX BIT(3)
2076 +#define MTK_PHY_LED_BLINK_10TX BIT(4)
2077 +#define MTK_PHY_LED_BLINK_10RX BIT(5)
2078 +#define MTK_PHY_LED_BLINK_RX (MTK_PHY_LED_BLINK_10RX |\
2079 + MTK_PHY_LED_BLINK_100RX |\
2080 + MTK_PHY_LED_BLINK_1000RX)
2081 +#define MTK_PHY_LED_BLINK_TX (MTK_PHY_LED_BLINK_10TX |\
2082 + MTK_PHY_LED_BLINK_100TX |\
2083 + MTK_PHY_LED_BLINK_1000TX)
2084 +#define MTK_PHY_LED_BLINK_COLLISION BIT(6)
2085 +#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
2086 +#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
2087 +#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9)
2088 +
2089 +#define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1)
2090 +
2091 +#define MTK_PHY_RG_BG_RASEL 0x115
2092 +#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
2093 +
2094 +/* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */
2095 +#define RG_GPIO_MISC_TPBANK0 0x6f0
2096 +#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8)
2097 +
2098 +/* These macro privides efuse parsing for internal phy. */
2099 +#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
2100 +#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
2101 +#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0))
2102 +#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0))
2103 +#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0))
2104 +
2105 +#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0))
2106 +#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0))
2107 +#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0))
2108 +#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0))
2109 +#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0))
2110 +
2111 +#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0))
2112 +#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0))
2113 +
2114 +#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0))
2115 +#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0))
2116 +
2117 +enum {
2118 + NO_PAIR,
2119 + PAIR_A,
2120 + PAIR_B,
2121 + PAIR_C,
2122 + PAIR_D,
2123 +};
2124 +
2125 +enum calibration_mode {
2126 + EFUSE_K,
2127 + SW_K
2128 +};
2129 +
2130 +enum CAL_ITEM {
2131 + REXT,
2132 + TX_OFFSET,
2133 + TX_AMP,
2134 + TX_R50,
2135 + TX_VCM
2136 +};
2137 +
2138 +enum CAL_MODE {
2139 + EFUSE_M,
2140 + SW_M
2141 +};
2142 +
2143 +#define MTK_PHY_LED_STATE_FORCE_ON 0
2144 +#define MTK_PHY_LED_STATE_FORCE_BLINK 1
2145 +#define MTK_PHY_LED_STATE_NETDEV 2
2146 +
2147 +struct mtk_socphy_priv {
2148 + unsigned long led_state;
2149 +};
2150 +
2151 +struct mtk_socphy_shared {
2152 + u32 boottrap;
2153 + struct mtk_socphy_priv priv[4];
2154 +};
2155 +
2156 +static int mtk_socphy_read_page(struct phy_device *phydev)
2157 +{
2158 + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
2159 +}
2160 +
2161 +static int mtk_socphy_write_page(struct phy_device *phydev, int page)
2162 +{
2163 + return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
2164 +}
2165 +
2166 +/* One calibration cycle consists of:
2167 + * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
2168 + * until AD_CAL_COMP is ready to output calibration result.
2169 + * 2.Wait until DA_CAL_CLK is available.
2170 + * 3.Fetch AD_CAL_COMP_OUT.
2171 + */
2172 +static int cal_cycle(struct phy_device *phydev, int devad,
2173 + u32 regnum, u16 mask, u16 cal_val)
2174 +{
2175 + int reg_val;
2176 + int ret;
2177 +
2178 + phy_modify_mmd(phydev, devad, regnum,
2179 + mask, cal_val);
2180 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
2181 + MTK_PHY_DA_CALIN_FLAG);
2182 +
2183 + ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
2184 + MTK_PHY_RG_AD_CAL_CLK, reg_val,
2185 + reg_val & MTK_PHY_DA_CAL_CLK, 500,
2186 + ANALOG_INTERNAL_OPERATION_MAX_US,
2187 + false);
2188 + if (ret) {
2189 + phydev_err(phydev, "Calibration cycle timeout\n");
2190 + return ret;
2191 + }
2192 +
2193 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
2194 + MTK_PHY_DA_CALIN_FLAG);
2195 + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP);
2196 + if (ret < 0)
2197 + return ret;
2198 + ret = FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret);
2199 + phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
2200 +
2201 + return ret;
2202 +}
2203 +
2204 +static int rext_fill_result(struct phy_device *phydev, u16 *buf)
2205 +{
2206 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
2207 + MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
2208 + phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
2209 + MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
2210 +
2211 + return 0;
2212 +}
2213 +
2214 +static int rext_cal_efuse(struct phy_device *phydev, u32 *buf)
2215 +{
2216 + u16 rext_cal_val[2];
2217 +
2218 + rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]);
2219 + rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]);
2220 + rext_fill_result(phydev, rext_cal_val);
2221 +
2222 + return 0;
2223 +}
2224 +
2225 +static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
2226 +{
2227 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
2228 + MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8);
2229 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
2230 + MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]);
2231 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
2232 + MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8);
2233 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
2234 + MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]);
2235 +
2236 + return 0;
2237 +}
2238 +
2239 +static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
2240 +{
2241 + u16 tx_offset_cal_val[4];
2242 +
2243 + tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]);
2244 + tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]);
2245 + tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]);
2246 + tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]);
2247 +
2248 + tx_offset_fill_result(phydev, tx_offset_cal_val);
2249 +
2250 + return 0;
2251 +}
2252 +
2253 +static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
2254 +{
2255 + const int vals_9481[16] = { 10, 6, 6, 10,
2256 + 10, 6, 6, 10,
2257 + 10, 6, 6, 10,
2258 + 10, 6, 6, 10 };
2259 + const int vals_9461[16] = { 7, 1, 4, 7,
2260 + 7, 1, 4, 7,
2261 + 7, 1, 4, 7,
2262 + 7, 1, 4, 7 };
2263 + int bias[16] = {};
2264 + int i;
2265 +
2266 + switch (phydev->drv->phy_id) {
2267 + case MTK_GPHY_ID_MT7981:
2268 + /* We add some calibration to efuse values
2269 + * due to board level influence.
2270 + * GBE: +7, TBT: +1, HBT: +4, TST: +7
2271 + */
2272 + memcpy(bias, (const void *)vals_9461, sizeof(bias));
2273 + break;
2274 + case MTK_GPHY_ID_MT7988:
2275 + memcpy(bias, (const void *)vals_9481, sizeof(bias));
2276 + break;
2277 + }
2278 +
2279 + /* Prevent overflow */
2280 + for (i = 0; i < 12; i++) {
2281 + if (buf[i >> 2] + bias[i] > 63) {
2282 + buf[i >> 2] = 63;
2283 + bias[i] = 0;
2284 + }
2285 + }
2286 +
2287 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
2288 + MTK_PHY_DA_TX_I2MPB_A_GBE_MASK,
2289 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_GBE_MASK,
2290 + buf[0] + bias[0]));
2291 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
2292 + MTK_PHY_DA_TX_I2MPB_A_TBT_MASK,
2293 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TBT_MASK,
2294 + buf[0] + bias[1]));
2295 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
2296 + MTK_PHY_DA_TX_I2MPB_A_HBT_MASK,
2297 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_HBT_MASK,
2298 + buf[0] + bias[2]));
2299 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
2300 + MTK_PHY_DA_TX_I2MPB_A_TST_MASK,
2301 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TST_MASK,
2302 + buf[0] + bias[3]));
2303 +
2304 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
2305 + MTK_PHY_DA_TX_I2MPB_B_GBE_MASK,
2306 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_GBE_MASK,
2307 + buf[1] + bias[4]));
2308 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
2309 + MTK_PHY_DA_TX_I2MPB_B_TBT_MASK,
2310 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TBT_MASK,
2311 + buf[1] + bias[5]));
2312 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
2313 + MTK_PHY_DA_TX_I2MPB_B_HBT_MASK,
2314 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_HBT_MASK,
2315 + buf[1] + bias[6]));
2316 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
2317 + MTK_PHY_DA_TX_I2MPB_B_TST_MASK,
2318 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TST_MASK,
2319 + buf[1] + bias[7]));
2320 +
2321 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
2322 + MTK_PHY_DA_TX_I2MPB_C_GBE_MASK,
2323 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_GBE_MASK,
2324 + buf[2] + bias[8]));
2325 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
2326 + MTK_PHY_DA_TX_I2MPB_C_TBT_MASK,
2327 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TBT_MASK,
2328 + buf[2] + bias[9]));
2329 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
2330 + MTK_PHY_DA_TX_I2MPB_C_HBT_MASK,
2331 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_HBT_MASK,
2332 + buf[2] + bias[10]));
2333 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
2334 + MTK_PHY_DA_TX_I2MPB_C_TST_MASK,
2335 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TST_MASK,
2336 + buf[2] + bias[11]));
2337 +
2338 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
2339 + MTK_PHY_DA_TX_I2MPB_D_GBE_MASK,
2340 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_GBE_MASK,
2341 + buf[3] + bias[12]));
2342 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
2343 + MTK_PHY_DA_TX_I2MPB_D_TBT_MASK,
2344 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TBT_MASK,
2345 + buf[3] + bias[13]));
2346 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
2347 + MTK_PHY_DA_TX_I2MPB_D_HBT_MASK,
2348 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_HBT_MASK,
2349 + buf[3] + bias[14]));
2350 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
2351 + MTK_PHY_DA_TX_I2MPB_D_TST_MASK,
2352 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TST_MASK,
2353 + buf[3] + bias[15]));
2354 +
2355 + return 0;
2356 +}
2357 +
2358 +static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf)
2359 +{
2360 + u16 tx_amp_cal_val[4];
2361 +
2362 + tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]);
2363 + tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]);
2364 + tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]);
2365 + tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]);
2366 + tx_amp_fill_result(phydev, tx_amp_cal_val);
2367 +
2368 + return 0;
2369 +}
2370 +
2371 +static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
2372 + u8 txg_calen_x)
2373 +{
2374 + int bias = 0;
2375 + u16 reg, val;
2376 +
2377 + if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
2378 + bias = -1;
2379 +
2380 + val = clamp_val(bias + tx_r50_cal_val, 0, 63);
2381 +
2382 + switch (txg_calen_x) {
2383 + case PAIR_A:
2384 + reg = MTK_PHY_DA_TX_R50_PAIR_A;
2385 + break;
2386 + case PAIR_B:
2387 + reg = MTK_PHY_DA_TX_R50_PAIR_B;
2388 + break;
2389 + case PAIR_C:
2390 + reg = MTK_PHY_DA_TX_R50_PAIR_C;
2391 + break;
2392 + case PAIR_D:
2393 + reg = MTK_PHY_DA_TX_R50_PAIR_D;
2394 + break;
2395 + default:
2396 + return -EINVAL;
2397 + }
2398 +
2399 + phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
2400 +
2401 + return 0;
2402 +}
2403 +
2404 +static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
2405 + u8 txg_calen_x)
2406 +{
2407 + u16 tx_r50_cal_val;
2408 +
2409 + switch (txg_calen_x) {
2410 + case PAIR_A:
2411 + tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]);
2412 + break;
2413 + case PAIR_B:
2414 + tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]);
2415 + break;
2416 + case PAIR_C:
2417 + tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]);
2418 + break;
2419 + case PAIR_D:
2420 + tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]);
2421 + break;
2422 + default:
2423 + return -EINVAL;
2424 + }
2425 + tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
2426 +
2427 + return 0;
2428 +}
2429 +
2430 +static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
2431 +{
2432 + u8 lower_idx, upper_idx, txreserve_val;
2433 + u8 lower_ret, upper_ret;
2434 + int ret;
2435 +
2436 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
2437 + MTK_PHY_RG_ANA_CALEN);
2438 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
2439 + MTK_PHY_RG_CAL_CKINV);
2440 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
2441 + MTK_PHY_RG_TXVOS_CALEN);
2442 +
2443 + switch (rg_txreserve_x) {
2444 + case PAIR_A:
2445 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2446 + MTK_PHY_RG_DASN_DAC_IN0_A,
2447 + MTK_PHY_DASN_DAC_IN0_A_MASK);
2448 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2449 + MTK_PHY_RG_DASN_DAC_IN1_A,
2450 + MTK_PHY_DASN_DAC_IN1_A_MASK);
2451 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
2452 + MTK_PHY_RG_ANA_CAL_RG0,
2453 + MTK_PHY_RG_ZCALEN_A);
2454 + break;
2455 + case PAIR_B:
2456 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2457 + MTK_PHY_RG_DASN_DAC_IN0_B,
2458 + MTK_PHY_DASN_DAC_IN0_B_MASK);
2459 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2460 + MTK_PHY_RG_DASN_DAC_IN1_B,
2461 + MTK_PHY_DASN_DAC_IN1_B_MASK);
2462 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
2463 + MTK_PHY_RG_ANA_CAL_RG1,
2464 + MTK_PHY_RG_ZCALEN_B);
2465 + break;
2466 + case PAIR_C:
2467 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2468 + MTK_PHY_RG_DASN_DAC_IN0_C,
2469 + MTK_PHY_DASN_DAC_IN0_C_MASK);
2470 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2471 + MTK_PHY_RG_DASN_DAC_IN1_C,
2472 + MTK_PHY_DASN_DAC_IN1_C_MASK);
2473 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
2474 + MTK_PHY_RG_ANA_CAL_RG1,
2475 + MTK_PHY_RG_ZCALEN_C);
2476 + break;
2477 + case PAIR_D:
2478 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2479 + MTK_PHY_RG_DASN_DAC_IN0_D,
2480 + MTK_PHY_DASN_DAC_IN0_D_MASK);
2481 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2482 + MTK_PHY_RG_DASN_DAC_IN1_D,
2483 + MTK_PHY_DASN_DAC_IN1_D_MASK);
2484 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
2485 + MTK_PHY_RG_ANA_CAL_RG1,
2486 + MTK_PHY_RG_ZCALEN_D);
2487 + break;
2488 + default:
2489 + ret = -EINVAL;
2490 + goto restore;
2491 + }
2492 +
2493 + lower_idx = TXRESERVE_MIN;
2494 + upper_idx = TXRESERVE_MAX;
2495 +
2496 + phydev_dbg(phydev, "Start TX-VCM SW cal.\n");
2497 + while ((upper_idx - lower_idx) > 1) {
2498 + txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2);
2499 + ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
2500 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
2501 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
2502 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
2503 + MTK_PHY_DA_RX_PSBN_LP_MASK,
2504 + txreserve_val << 12 | txreserve_val << 8 |
2505 + txreserve_val << 4 | txreserve_val);
2506 + if (ret == 1) {
2507 + upper_idx = txreserve_val;
2508 + upper_ret = ret;
2509 + } else if (ret == 0) {
2510 + lower_idx = txreserve_val;
2511 + lower_ret = ret;
2512 + } else {
2513 + goto restore;
2514 + }
2515 + }
2516 +
2517 + if (lower_idx == TXRESERVE_MIN) {
2518 + lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
2519 + MTK_PHY_RXADC_CTRL_RG9,
2520 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
2521 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
2522 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
2523 + MTK_PHY_DA_RX_PSBN_LP_MASK,
2524 + lower_idx << 12 | lower_idx << 8 |
2525 + lower_idx << 4 | lower_idx);
2526 + ret = lower_ret;
2527 + } else if (upper_idx == TXRESERVE_MAX) {
2528 + upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
2529 + MTK_PHY_RXADC_CTRL_RG9,
2530 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
2531 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
2532 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
2533 + MTK_PHY_DA_RX_PSBN_LP_MASK,
2534 + upper_idx << 12 | upper_idx << 8 |
2535 + upper_idx << 4 | upper_idx);
2536 + ret = upper_ret;
2537 + }
2538 + if (ret < 0)
2539 + goto restore;
2540 +
2541 + /* We calibrate TX-VCM in different logic. Check upper index and then
2542 + * lower index. If this calibration is valid, apply lower index's
2543 + * result.
2544 + */
2545 + ret = upper_ret - lower_ret;
2546 + if (ret == 1) {
2547 + ret = 0;
2548 + /* Make sure we use upper_idx in our calibration system */
2549 + cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
2550 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
2551 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
2552 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
2553 + MTK_PHY_DA_RX_PSBN_LP_MASK,
2554 + upper_idx << 12 | upper_idx << 8 |
2555 + upper_idx << 4 | upper_idx);
2556 + phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
2557 + } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
2558 + lower_ret == 1) {
2559 + ret = 0;
2560 + cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
2561 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
2562 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
2563 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
2564 + MTK_PHY_DA_RX_PSBN_LP_MASK,
2565 + lower_idx << 12 | lower_idx << 8 |
2566 + lower_idx << 4 | lower_idx);
2567 + phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n",
2568 + lower_idx);
2569 + } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
2570 + lower_ret == 0) {
2571 + ret = 0;
2572 + phydev_warn(phydev,
2573 + "TX-VCM SW cal result at high margin 0x%x\n",
2574 + upper_idx);
2575 + } else {
2576 + ret = -EINVAL;
2577 + }
2578 +
2579 +restore:
2580 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
2581 + MTK_PHY_RG_ANA_CALEN);
2582 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
2583 + MTK_PHY_RG_TXVOS_CALEN);
2584 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
2585 + MTK_PHY_RG_ZCALEN_A);
2586 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
2587 + MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C |
2588 + MTK_PHY_RG_ZCALEN_D);
2589 +
2590 + return ret;
2591 +}
2592 +
2593 +static void mt798x_phy_common_finetune(struct phy_device *phydev)
2594 +{
2595 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
2596 + /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
2597 + __phy_write(phydev, 0x11, 0xc71);
2598 + __phy_write(phydev, 0x12, 0xc);
2599 + __phy_write(phydev, 0x10, 0x8fae);
2600 +
2601 + /* EnabRandUpdTrig = 1 */
2602 + __phy_write(phydev, 0x11, 0x2f00);
2603 + __phy_write(phydev, 0x12, 0xe);
2604 + __phy_write(phydev, 0x10, 0x8fb0);
2605 +
2606 + /* NormMseLoThresh = 85 */
2607 + __phy_write(phydev, 0x11, 0x55a0);
2608 + __phy_write(phydev, 0x12, 0x0);
2609 + __phy_write(phydev, 0x10, 0x83aa);
2610 +
2611 + /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
2612 + __phy_write(phydev, 0x11, 0x240);
2613 + __phy_write(phydev, 0x12, 0x0);
2614 + __phy_write(phydev, 0x10, 0x9680);
2615 +
2616 + /* TrFreeze = 0 (mt7988 default) */
2617 + __phy_write(phydev, 0x11, 0x0);
2618 + __phy_write(phydev, 0x12, 0x0);
2619 + __phy_write(phydev, 0x10, 0x9686);
2620 +
2621 + /* SSTrKp100 = 5 */
2622 + /* SSTrKf100 = 6 */
2623 + /* SSTrKp1000Mas = 5 */
2624 + /* SSTrKf1000Mas = 6 */
2625 + /* SSTrKp1000Slv = 5 */
2626 + /* SSTrKf1000Slv = 6 */
2627 + __phy_write(phydev, 0x11, 0xbaef);
2628 + __phy_write(phydev, 0x12, 0x2e);
2629 + __phy_write(phydev, 0x10, 0x968c);
2630 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
2631 +}
2632 +
2633 +static void mt7981_phy_finetune(struct phy_device *phydev)
2634 +{
2635 + u16 val[8] = { 0x01ce, 0x01c1,
2636 + 0x020f, 0x0202,
2637 + 0x03d0, 0x03c0,
2638 + 0x0013, 0x0005 };
2639 + int i, k;
2640 +
2641 + /* 100M eye finetune:
2642 + * Keep middle level of TX MLT3 shapper as default.
2643 + * Only change TX MLT3 overshoot level here.
2644 + */
2645 + for (k = 0, i = 1; i < 12; i++) {
2646 + if (i % 3 == 0)
2647 + continue;
2648 + phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
2649 + }
2650 +
2651 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
2652 + /* ResetSyncOffset = 6 */
2653 + __phy_write(phydev, 0x11, 0x600);
2654 + __phy_write(phydev, 0x12, 0x0);
2655 + __phy_write(phydev, 0x10, 0x8fc0);
2656 +
2657 + /* VgaDecRate = 1 */
2658 + __phy_write(phydev, 0x11, 0x4c2a);
2659 + __phy_write(phydev, 0x12, 0x3e);
2660 + __phy_write(phydev, 0x10, 0x8fa4);
2661 +
2662 + /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
2663 + * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
2664 + */
2665 + __phy_write(phydev, 0x11, 0xd10a);
2666 + __phy_write(phydev, 0x12, 0x34);
2667 + __phy_write(phydev, 0x10, 0x8f82);
2668 +
2669 + /* VcoSlicerThreshBitsHigh */
2670 + __phy_write(phydev, 0x11, 0x5555);
2671 + __phy_write(phydev, 0x12, 0x55);
2672 + __phy_write(phydev, 0x10, 0x8ec0);
2673 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
2674 +
2675 + /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
2676 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
2677 + MTK_PHY_TR_OPEN_LOOP_EN_MASK |
2678 + MTK_PHY_LPF_X_AVERAGE_MASK,
2679 + BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
2680 +
2681 + /* rg_tr_lpf_cnt_val = 512 */
2682 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
2683 +
2684 + /* IIR2 related */
2685 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
2686 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
2687 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
2688 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
2689 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
2690 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
2691 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
2692 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
2693 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
2694 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
2695 +
2696 + /* FFE peaking */
2697 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
2698 + MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
2699 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
2700 + MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
2701 +
2702 + /* Disable LDO pump */
2703 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
2704 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
2705 + /* Adjust LDO output voltage */
2706 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
2707 +}
2708 +
2709 +static void mt7988_phy_finetune(struct phy_device *phydev)
2710 +{
2711 + u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
2712 + 0x020d, 0x0206, 0x0384, 0x03d0,
2713 + 0x03c6, 0x030a, 0x0011, 0x0005 };
2714 + int i;
2715 +
2716 + /* Set default MLT3 shaper first */
2717 + for (i = 0; i < 12; i++)
2718 + phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
2719 +
2720 + /* TCT finetune */
2721 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
2722 +
2723 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
2724 + /* ResetSyncOffset = 5 */
2725 + __phy_write(phydev, 0x11, 0x500);
2726 + __phy_write(phydev, 0x12, 0x0);
2727 + __phy_write(phydev, 0x10, 0x8fc0);
2728 +
2729 + /* VgaDecRate is 1 at default on mt7988 */
2730 +
2731 + /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
2732 + * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
2733 + */
2734 + __phy_write(phydev, 0x11, 0xb90a);
2735 + __phy_write(phydev, 0x12, 0x6f);
2736 + __phy_write(phydev, 0x10, 0x8f82);
2737 +
2738 + /* RemAckCntLimitCtrl = 1 */
2739 + __phy_write(phydev, 0x11, 0xfbba);
2740 + __phy_write(phydev, 0x12, 0xc3);
2741 + __phy_write(phydev, 0x10, 0x87f8);
2742 +
2743 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
2744 +
2745 + /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
2746 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
2747 + MTK_PHY_TR_OPEN_LOOP_EN_MASK |
2748 + MTK_PHY_LPF_X_AVERAGE_MASK,
2749 + BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
2750 +
2751 + /* rg_tr_lpf_cnt_val = 1023 */
2752 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
2753 +}
2754 +
2755 +static void mt798x_phy_eee(struct phy_device *phydev)
2756 +{
2757 + phy_modify_mmd(phydev, MDIO_MMD_VEND1,
2758 + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120,
2759 + MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK |
2760 + MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK,
2761 + FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) |
2762 + FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14));
2763 +
2764 + phy_modify_mmd(phydev, MDIO_MMD_VEND1,
2765 + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
2766 + MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
2767 + FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
2768 + 0xff));
2769 +
2770 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2771 + MTK_PHY_RG_TESTMUX_ADC_CTRL,
2772 + MTK_PHY_RG_TXEN_DIG_MASK);
2773 +
2774 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
2775 + MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY);
2776 +
2777 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2778 + MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN);
2779 +
2780 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
2781 + MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK |
2782 + MTK_PHY_LPI_SLV_SEND_TX_EN,
2783 + FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
2784 +
2785 + /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */
2786 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
2787 + MTK_PHY_LPI_TXPCS_LOC_RCV);
2788 +
2789 + /* This also fixes some IoT issues, such as CH340 */
2790 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
2791 + MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
2792 + FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
2793 + FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13));
2794 +
2795 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
2796 + MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
2797 + FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
2798 + 0x33) |
2799 + MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY |
2800 + MTK_PHY_LPI_VCO_EEE_STG0_EN);
2801 +
2802 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
2803 + MTK_PHY_EEE_WAKE_MAS_INT_DC |
2804 + MTK_PHY_EEE_WAKE_SLV_INT_DC);
2805 +
2806 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
2807 + MTK_PHY_SMI_DETCNT_MAX_MASK,
2808 + FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) |
2809 + MTK_PHY_SMI_DET_MAX_EN);
2810 +
2811 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
2812 + MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT |
2813 + MTK_PHY_TREC_UPDATE_ENAB_CLR |
2814 + MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF |
2815 + MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
2816 +
2817 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
2818 + /* Regsigdet_sel_1000 = 0 */
2819 + __phy_write(phydev, 0x11, 0xb);
2820 + __phy_write(phydev, 0x12, 0x0);
2821 + __phy_write(phydev, 0x10, 0x9690);
2822 +
2823 + /* REG_EEE_st2TrKf1000 = 2 */
2824 + __phy_write(phydev, 0x11, 0x114f);
2825 + __phy_write(phydev, 0x12, 0x2);
2826 + __phy_write(phydev, 0x10, 0x969a);
2827 +
2828 + /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
2829 + __phy_write(phydev, 0x11, 0x3028);
2830 + __phy_write(phydev, 0x12, 0x0);
2831 + __phy_write(phydev, 0x10, 0x969e);
2832 +
2833 + /* RegEEE_slv_wake_int_timer_tar = 8 */
2834 + __phy_write(phydev, 0x11, 0x5010);
2835 + __phy_write(phydev, 0x12, 0x0);
2836 + __phy_write(phydev, 0x10, 0x96a0);
2837 +
2838 + /* RegEEE_trfreeze_timer2 = 586 */
2839 + __phy_write(phydev, 0x11, 0x24a);
2840 + __phy_write(phydev, 0x12, 0x0);
2841 + __phy_write(phydev, 0x10, 0x96a8);
2842 +
2843 + /* RegEEE100Stg1_tar = 16 */
2844 + __phy_write(phydev, 0x11, 0x3210);
2845 + __phy_write(phydev, 0x12, 0x0);
2846 + __phy_write(phydev, 0x10, 0x96b8);
2847 +
2848 + /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
2849 + __phy_write(phydev, 0x11, 0x1463);
2850 + __phy_write(phydev, 0x12, 0x0);
2851 + __phy_write(phydev, 0x10, 0x96ca);
2852 +
2853 + /* DfeTailEnableVgaThresh1000 = 27 */
2854 + __phy_write(phydev, 0x11, 0x36);
2855 + __phy_write(phydev, 0x12, 0x0);
2856 + __phy_write(phydev, 0x10, 0x8f80);
2857 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
2858 +
2859 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
2860 + __phy_modify(phydev, MTK_PHY_LPI_REG_14,
2861 + MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
2862 + FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
2863 +
2864 + __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
2865 + FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc));
2866 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
2867 +
2868 + phy_modify_mmd(phydev, MDIO_MMD_VEND1,
2869 + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
2870 + MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
2871 + FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
2872 + 0xff));
2873 +}
2874 +
2875 +static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
2876 + u8 start_pair, u8 end_pair)
2877 +{
2878 + u8 pair_n;
2879 + int ret;
2880 +
2881 + for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
2882 + /* TX_OFFSET & TX_AMP have no SW calibration. */
2883 + switch (cal_item) {
2884 + case TX_VCM:
2885 + ret = tx_vcm_cal_sw(phydev, pair_n);
2886 + break;
2887 + default:
2888 + return -EINVAL;
2889 + }
2890 + if (ret)
2891 + return ret;
2892 + }
2893 + return 0;
2894 +}
2895 +
2896 +static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
2897 + u8 start_pair, u8 end_pair, u32 *buf)
2898 +{
2899 + u8 pair_n;
2900 + int ret;
2901 +
2902 + for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
2903 + /* TX_VCM has no efuse calibration. */
2904 + switch (cal_item) {
2905 + case REXT:
2906 + ret = rext_cal_efuse(phydev, buf);
2907 + break;
2908 + case TX_OFFSET:
2909 + ret = tx_offset_cal_efuse(phydev, buf);
2910 + break;
2911 + case TX_AMP:
2912 + ret = tx_amp_cal_efuse(phydev, buf);
2913 + break;
2914 + case TX_R50:
2915 + ret = tx_r50_cal_efuse(phydev, buf, pair_n);
2916 + break;
2917 + default:
2918 + return -EINVAL;
2919 + }
2920 + if (ret)
2921 + return ret;
2922 + }
2923 +
2924 + return 0;
2925 +}
2926 +
2927 +static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
2928 + enum CAL_MODE cal_mode, u8 start_pair,
2929 + u8 end_pair, u32 *buf)
2930 +{
2931 + int ret;
2932 +
2933 + switch (cal_mode) {
2934 + case EFUSE_M:
2935 + ret = cal_efuse(phydev, cal_item, start_pair,
2936 + end_pair, buf);
2937 + break;
2938 + case SW_M:
2939 + ret = cal_sw(phydev, cal_item, start_pair, end_pair);
2940 + break;
2941 + default:
2942 + return -EINVAL;
2943 + }
2944 +
2945 + if (ret) {
2946 + phydev_err(phydev, "cal %d failed\n", cal_item);
2947 + return -EIO;
2948 + }
2949 +
2950 + return 0;
2951 +}
2952 +
2953 +static int mt798x_phy_calibration(struct phy_device *phydev)
2954 +{
2955 + struct nvmem_cell *cell;
2956 + int ret = 0;
2957 + size_t len;
2958 + u32 *buf;
2959 +
2960 + cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
2961 + if (IS_ERR(cell)) {
2962 + if (PTR_ERR(cell) == -EPROBE_DEFER)
2963 + return PTR_ERR(cell);
2964 + return 0;
2965 + }
2966 +
2967 + buf = (u32 *)nvmem_cell_read(cell, &len);
2968 + if (IS_ERR(buf))
2969 + return PTR_ERR(buf);
2970 + nvmem_cell_put(cell);
2971 +
2972 + if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) {
2973 + phydev_err(phydev, "invalid efuse data\n");
2974 + ret = -EINVAL;
2975 + goto out;
2976 + }
2977 +
2978 + ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf);
2979 + if (ret)
2980 + goto out;
2981 + ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf);
2982 + if (ret)
2983 + goto out;
2984 + ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf);
2985 + if (ret)
2986 + goto out;
2987 + ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf);
2988 + if (ret)
2989 + goto out;
2990 + ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf);
2991 + if (ret)
2992 + goto out;
2993 +
2994 +out:
2995 + kfree(buf);
2996 + return ret;
2997 +}
2998 +
2999 +static int mt798x_phy_config_init(struct phy_device *phydev)
3000 +{
3001 + switch (phydev->drv->phy_id) {
3002 + case MTK_GPHY_ID_MT7981:
3003 + mt7981_phy_finetune(phydev);
3004 + break;
3005 + case MTK_GPHY_ID_MT7988:
3006 + mt7988_phy_finetune(phydev);
3007 + break;
3008 + }
3009 +
3010 + mt798x_phy_common_finetune(phydev);
3011 + mt798x_phy_eee(phydev);
3012 +
3013 + return mt798x_phy_calibration(phydev);
3014 +}
3015 +
3016 +static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
3017 + bool on)
3018 +{
3019 + unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
3020 + struct mtk_socphy_priv *priv = phydev->priv;
3021 + bool changed;
3022 +
3023 + if (on)
3024 + changed = !test_and_set_bit(bit_on, &priv->led_state);
3025 + else
3026 + changed = !!test_and_clear_bit(bit_on, &priv->led_state);
3027 +
3028 + changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV +
3029 + (index ? 16 : 0), &priv->led_state);
3030 + if (changed)
3031 + return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
3032 + MTK_PHY_LED1_ON_CTRL :
3033 + MTK_PHY_LED0_ON_CTRL,
3034 + MTK_PHY_LED_ON_MASK,
3035 + on ? MTK_PHY_LED_ON_FORCE_ON : 0);
3036 + else
3037 + return 0;
3038 +}
3039 +
3040 +static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
3041 + bool blinking)
3042 +{
3043 + unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
3044 + (index ? 16 : 0);
3045 + struct mtk_socphy_priv *priv = phydev->priv;
3046 + bool changed;
3047 +
3048 + if (blinking)
3049 + changed = !test_and_set_bit(bit_blink, &priv->led_state);
3050 + else
3051 + changed = !!test_and_clear_bit(bit_blink, &priv->led_state);
3052 +
3053 + changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV +
3054 + (index ? 16 : 0), &priv->led_state);
3055 + if (changed)
3056 + return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
3057 + MTK_PHY_LED1_BLINK_CTRL :
3058 + MTK_PHY_LED0_BLINK_CTRL,
3059 + blinking ?
3060 + MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
3061 + else
3062 + return 0;
3063 +}
3064 +
3065 +static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
3066 + unsigned long *delay_on,
3067 + unsigned long *delay_off)
3068 +{
3069 + bool blinking = false;
3070 + int err = 0;
3071 +
3072 + if (index > 1)
3073 + return -EINVAL;
3074 +
3075 + if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
3076 + blinking = true;
3077 + *delay_on = 50;
3078 + *delay_off = 50;
3079 + }
3080 +
3081 + err = mt798x_phy_hw_led_blink_set(phydev, index, blinking);
3082 + if (err)
3083 + return err;
3084 +
3085 + return mt798x_phy_hw_led_on_set(phydev, index, false);
3086 +}
3087 +
3088 +static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
3089 + u8 index, enum led_brightness value)
3090 +{
3091 + int err;
3092 +
3093 + err = mt798x_phy_hw_led_blink_set(phydev, index, false);
3094 + if (err)
3095 + return err;
3096 +
3097 + return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF));
3098 +}
3099 +
3100 +static const unsigned long supported_triggers =
3101 + BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
3102 + BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
3103 + BIT(TRIGGER_NETDEV_LINK) |
3104 + BIT(TRIGGER_NETDEV_LINK_10) |
3105 + BIT(TRIGGER_NETDEV_LINK_100) |
3106 + BIT(TRIGGER_NETDEV_LINK_1000) |
3107 + BIT(TRIGGER_NETDEV_RX) |
3108 + BIT(TRIGGER_NETDEV_TX);
3109 +
3110 +static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
3111 + unsigned long rules)
3112 +{
3113 + if (index > 1)
3114 + return -EINVAL;
3115 +
3116 + /* All combinations of the supported triggers are allowed */
3117 + if (rules & ~supported_triggers)
3118 + return -EOPNOTSUPP;
3119 +
3120 + return 0;
3121 +};
3122 +
3123 +static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
3124 + unsigned long *rules)
3125 +{
3126 + unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
3127 + (index ? 16 : 0);
3128 + unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
3129 + unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
3130 + struct mtk_socphy_priv *priv = phydev->priv;
3131 + int on, blink;
3132 +
3133 + if (index > 1)
3134 + return -EINVAL;
3135 +
3136 + on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
3137 + index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL);
3138 +
3139 + if (on < 0)
3140 + return -EIO;
3141 +
3142 + blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
3143 + index ? MTK_PHY_LED1_BLINK_CTRL :
3144 + MTK_PHY_LED0_BLINK_CTRL);
3145 + if (blink < 0)
3146 + return -EIO;
3147 +
3148 + if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX |
3149 + MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) ||
3150 + (blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX)))
3151 + set_bit(bit_netdev, &priv->led_state);
3152 + else
3153 + clear_bit(bit_netdev, &priv->led_state);
3154 +
3155 + if (on & MTK_PHY_LED_ON_FORCE_ON)
3156 + set_bit(bit_on, &priv->led_state);
3157 + else
3158 + clear_bit(bit_on, &priv->led_state);
3159 +
3160 + if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK)
3161 + set_bit(bit_blink, &priv->led_state);
3162 + else
3163 + clear_bit(bit_blink, &priv->led_state);
3164 +
3165 + if (!rules)
3166 + return 0;
3167 +
3168 + if (on & MTK_PHY_LED_ON_LINK)
3169 + *rules |= BIT(TRIGGER_NETDEV_LINK);
3170 +
3171 + if (on & MTK_PHY_LED_ON_LINK10)
3172 + *rules |= BIT(TRIGGER_NETDEV_LINK_10);
3173 +
3174 + if (on & MTK_PHY_LED_ON_LINK100)
3175 + *rules |= BIT(TRIGGER_NETDEV_LINK_100);
3176 +
3177 + if (on & MTK_PHY_LED_ON_LINK1000)
3178 + *rules |= BIT(TRIGGER_NETDEV_LINK_1000);
3179 +
3180 + if (on & MTK_PHY_LED_ON_FDX)
3181 + *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
3182 +
3183 + if (on & MTK_PHY_LED_ON_HDX)
3184 + *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
3185 +
3186 + if (blink & MTK_PHY_LED_BLINK_RX)
3187 + *rules |= BIT(TRIGGER_NETDEV_RX);
3188 +
3189 + if (blink & MTK_PHY_LED_BLINK_TX)
3190 + *rules |= BIT(TRIGGER_NETDEV_TX);
3191 +
3192 + return 0;
3193 +};
3194 +
3195 +static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
3196 + unsigned long rules)
3197 +{
3198 + unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
3199 + struct mtk_socphy_priv *priv = phydev->priv;
3200 + u16 on = 0, blink = 0;
3201 + int ret;
3202 +
3203 + if (index > 1)
3204 + return -EINVAL;
3205 +
3206 + if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
3207 + on |= MTK_PHY_LED_ON_FDX;
3208 +
3209 + if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
3210 + on |= MTK_PHY_LED_ON_HDX;
3211 +
3212 + if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
3213 + on |= MTK_PHY_LED_ON_LINK10;
3214 +
3215 + if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
3216 + on |= MTK_PHY_LED_ON_LINK100;
3217 +
3218 + if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
3219 + on |= MTK_PHY_LED_ON_LINK1000;
3220 +
3221 + if (rules & BIT(TRIGGER_NETDEV_RX)) {
3222 + blink |= (on & MTK_PHY_LED_ON_LINK) ?
3223 + (((on & MTK_PHY_LED_ON_LINK10) ?
3224 + MTK_PHY_LED_BLINK_10RX : 0) |
3225 + ((on & MTK_PHY_LED_ON_LINK100) ?
3226 + MTK_PHY_LED_BLINK_100RX : 0) |
3227 + ((on & MTK_PHY_LED_ON_LINK1000) ?
3228 + MTK_PHY_LED_BLINK_1000RX : 0)) :
3229 + MTK_PHY_LED_BLINK_RX;
3230 + }
3231 +
3232 + if (rules & BIT(TRIGGER_NETDEV_TX)) {
3233 + blink |= (on & MTK_PHY_LED_ON_LINK) ?
3234 + (((on & MTK_PHY_LED_ON_LINK10) ?
3235 + MTK_PHY_LED_BLINK_10TX : 0) |
3236 + ((on & MTK_PHY_LED_ON_LINK100) ?
3237 + MTK_PHY_LED_BLINK_100TX : 0) |
3238 + ((on & MTK_PHY_LED_ON_LINK1000) ?
3239 + MTK_PHY_LED_BLINK_1000TX : 0)) :
3240 + MTK_PHY_LED_BLINK_TX;
3241 + }
3242 +
3243 + if (blink || on)
3244 + set_bit(bit_netdev, &priv->led_state);
3245 + else
3246 + clear_bit(bit_netdev, &priv->led_state);
3247 +
3248 + ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
3249 + MTK_PHY_LED1_ON_CTRL :
3250 + MTK_PHY_LED0_ON_CTRL,
3251 + MTK_PHY_LED_ON_FDX |
3252 + MTK_PHY_LED_ON_HDX |
3253 + MTK_PHY_LED_ON_LINK,
3254 + on);
3255 +
3256 + if (ret)
3257 + return ret;
3258 +
3259 + return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
3260 + MTK_PHY_LED1_BLINK_CTRL :
3261 + MTK_PHY_LED0_BLINK_CTRL, blink);
3262 +};
3263 +
3264 +static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num)
3265 +{
3266 + struct mtk_socphy_shared *priv = phydev->shared->priv;
3267 + u32 polarities;
3268 +
3269 + if (led_num == 0)
3270 + polarities = ~(priv->boottrap);
3271 + else
3272 + polarities = MTK_PHY_LED1_DEFAULT_POLARITIES;
3273 +
3274 + if (polarities & BIT(phydev->mdio.addr))
3275 + return true;
3276 +
3277 + return false;
3278 +}
3279 +
3280 +static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev)
3281 +{
3282 + struct pinctrl *pinctrl;
3283 + int index;
3284 +
3285 + /* Setup LED polarity according to bootstrap use of LED pins */
3286 + for (index = 0; index < 2; ++index)
3287 + phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
3288 + MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
3289 + MTK_PHY_LED_ON_POLARITY,
3290 + mt7988_phy_led_get_polarity(phydev, index) ?
3291 + MTK_PHY_LED_ON_POLARITY : 0);
3292 +
3293 + /* Only now setup pinctrl to avoid bogus blinking */
3294 + pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
3295 + if (IS_ERR(pinctrl))
3296 + dev_err(&phydev->mdio.bus->dev,
3297 + "Failed to setup PHY LED pinctrl\n");
3298 +
3299 + return 0;
3300 +}
3301 +
3302 +static int mt7988_phy_probe_shared(struct phy_device *phydev)
3303 +{
3304 + struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
3305 + struct mtk_socphy_shared *shared = phydev->shared->priv;
3306 + struct regmap *regmap;
3307 + u32 reg;
3308 + int ret;
3309 +
3310 + /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B,
3311 + * LED_C and LED_D respectively. At the same time those pins are used to
3312 + * bootstrap configuration of the reference clock source (LED_A),
3313 + * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
3314 + * In practice this is done using a LED and a resistor pulling the pin
3315 + * either to GND or to VIO.
3316 + * The detected value at boot time is accessible at run-time using the
3317 + * TPBANK0 register located in the gpio base of the pinctrl, in order
3318 + * to read it here it needs to be referenced by a phandle called
3319 + * 'mediatek,pio' in the MDIO bus hosting the PHY.
3320 + * The 4 bits in TPBANK0 are kept as package shared data and are used to
3321 + * set LED polarity for each of the LED0.
3322 + */
3323 + regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio");
3324 + if (IS_ERR(regmap))
3325 + return PTR_ERR(regmap);
3326 +
3327 + ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, &reg);
3328 + if (ret)
3329 + return ret;
3330 +
3331 + shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg);
3332 +
3333 + return 0;
3334 +}
3335 +
3336 +static void mt798x_phy_leds_state_init(struct phy_device *phydev)
3337 +{
3338 + int i;
3339 +
3340 + for (i = 0; i < 2; ++i)
3341 + mt798x_phy_led_hw_control_get(phydev, i, NULL);
3342 +}
3343 +
3344 +static int mt7988_phy_probe(struct phy_device *phydev)
3345 +{
3346 + struct mtk_socphy_shared *shared;
3347 + struct mtk_socphy_priv *priv;
3348 + int err;
3349 +
3350 + if (phydev->mdio.addr > 3)
3351 + return -EINVAL;
3352 +
3353 + err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
3354 + sizeof(struct mtk_socphy_shared));
3355 + if (err)
3356 + return err;
3357 +
3358 + if (phy_package_probe_once(phydev)) {
3359 + err = mt7988_phy_probe_shared(phydev);
3360 + if (err)
3361 + return err;
3362 + }
3363 +
3364 + shared = phydev->shared->priv;
3365 + priv = &shared->priv[phydev->mdio.addr];
3366 +
3367 + phydev->priv = priv;
3368 +
3369 + mt798x_phy_leds_state_init(phydev);
3370 +
3371 + err = mt7988_phy_fix_leds_polarities(phydev);
3372 + if (err)
3373 + return err;
3374 +
3375 + /* Disable TX power saving at probing to:
3376 + * 1. Meet common mode compliance test criteria
3377 + * 2. Make sure that TX-VCM calibration works fine
3378 + */
3379 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
3380 + MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
3381 +
3382 + return mt798x_phy_calibration(phydev);
3383 +}
3384 +
3385 +static int mt7981_phy_probe(struct phy_device *phydev)
3386 +{
3387 + struct mtk_socphy_priv *priv;
3388 +
3389 + priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv),
3390 + GFP_KERNEL);
3391 + if (!priv)
3392 + return -ENOMEM;
3393 +
3394 + phydev->priv = priv;
3395 +
3396 + mt798x_phy_leds_state_init(phydev);
3397 +
3398 + return mt798x_phy_calibration(phydev);
3399 +}
3400 +
3401 +static struct phy_driver mtk_socphy_driver[] = {
3402 + {
3403 + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
3404 + .name = "MediaTek MT7981 PHY",
3405 + .config_init = mt798x_phy_config_init,
3406 + .config_intr = genphy_no_config_intr,
3407 + .handle_interrupt = genphy_handle_interrupt_no_ack,
3408 + .probe = mt7981_phy_probe,
3409 + .suspend = genphy_suspend,
3410 + .resume = genphy_resume,
3411 + .read_page = mtk_socphy_read_page,
3412 + .write_page = mtk_socphy_write_page,
3413 + .led_blink_set = mt798x_phy_led_blink_set,
3414 + .led_brightness_set = mt798x_phy_led_brightness_set,
3415 + .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
3416 + .led_hw_control_set = mt798x_phy_led_hw_control_set,
3417 + .led_hw_control_get = mt798x_phy_led_hw_control_get,
3418 + },
3419 + {
3420 + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
3421 + .name = "MediaTek MT7988 PHY",
3422 + .config_init = mt798x_phy_config_init,
3423 + .config_intr = genphy_no_config_intr,
3424 + .handle_interrupt = genphy_handle_interrupt_no_ack,
3425 + .probe = mt7988_phy_probe,
3426 + .suspend = genphy_suspend,
3427 + .resume = genphy_resume,
3428 + .read_page = mtk_socphy_read_page,
3429 + .write_page = mtk_socphy_write_page,
3430 + .led_blink_set = mt798x_phy_led_blink_set,
3431 + .led_brightness_set = mt798x_phy_led_brightness_set,
3432 + .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
3433 + .led_hw_control_set = mt798x_phy_led_hw_control_set,
3434 + .led_hw_control_get = mt798x_phy_led_hw_control_get,
3435 + },
3436 +};
3437 +
3438 +module_phy_driver(mtk_socphy_driver);
3439 +
3440 +static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
3441 + { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
3442 + { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
3443 + { }
3444 +};
3445 +
3446 +MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver");
3447 +MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
3448 +MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
3449 +MODULE_LICENSE("GPL");
3450 +
3451 +MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl);
3452 --- /dev/null
3453 +++ b/drivers/net/phy/mediatek/mtk-ge.c
3454 @@ -0,0 +1,111 @@
3455 +// SPDX-License-Identifier: GPL-2.0+
3456 +#include <linux/bitfield.h>
3457 +#include <linux/module.h>
3458 +#include <linux/phy.h>
3459 +
3460 +#define MTK_EXT_PAGE_ACCESS 0x1f
3461 +#define MTK_PHY_PAGE_STANDARD 0x0000
3462 +#define MTK_PHY_PAGE_EXTENDED 0x0001
3463 +#define MTK_PHY_PAGE_EXTENDED_2 0x0002
3464 +#define MTK_PHY_PAGE_EXTENDED_3 0x0003
3465 +#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
3466 +#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
3467 +
3468 +static int mtk_gephy_read_page(struct phy_device *phydev)
3469 +{
3470 + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
3471 +}
3472 +
3473 +static int mtk_gephy_write_page(struct phy_device *phydev, int page)
3474 +{
3475 + return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
3476 +}
3477 +
3478 +static void mtk_gephy_config_init(struct phy_device *phydev)
3479 +{
3480 + /* Enable HW auto downshift */
3481 + phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
3482 +
3483 + /* Increase SlvDPSready time */
3484 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
3485 + __phy_write(phydev, 0x10, 0xafae);
3486 + __phy_write(phydev, 0x12, 0x2f);
3487 + __phy_write(phydev, 0x10, 0x8fae);
3488 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
3489 +
3490 + /* Adjust 100_mse_threshold */
3491 + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
3492 +
3493 + /* Disable mcc */
3494 + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
3495 +}
3496 +
3497 +static int mt7530_phy_config_init(struct phy_device *phydev)
3498 +{
3499 + mtk_gephy_config_init(phydev);
3500 +
3501 + /* Increase post_update_timer */
3502 + phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
3503 +
3504 + return 0;
3505 +}
3506 +
3507 +static int mt7531_phy_config_init(struct phy_device *phydev)
3508 +{
3509 + mtk_gephy_config_init(phydev);
3510 +
3511 + /* PHY link down power saving enable */
3512 + phy_set_bits(phydev, 0x17, BIT(4));
3513 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
3514 +
3515 + /* Set TX Pair delay selection */
3516 + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
3517 + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
3518 +
3519 + return 0;
3520 +}
3521 +
3522 +static struct phy_driver mtk_gephy_driver[] = {
3523 + {
3524 + PHY_ID_MATCH_EXACT(0x03a29412),
3525 + .name = "MediaTek MT7530 PHY",
3526 + .config_init = mt7530_phy_config_init,
3527 + /* Interrupts are handled by the switch, not the PHY
3528 + * itself.
3529 + */
3530 + .config_intr = genphy_no_config_intr,
3531 + .handle_interrupt = genphy_handle_interrupt_no_ack,
3532 + .suspend = genphy_suspend,
3533 + .resume = genphy_resume,
3534 + .read_page = mtk_gephy_read_page,
3535 + .write_page = mtk_gephy_write_page,
3536 + },
3537 + {
3538 + PHY_ID_MATCH_EXACT(0x03a29441),
3539 + .name = "MediaTek MT7531 PHY",
3540 + .config_init = mt7531_phy_config_init,
3541 + /* Interrupts are handled by the switch, not the PHY
3542 + * itself.
3543 + */
3544 + .config_intr = genphy_no_config_intr,
3545 + .handle_interrupt = genphy_handle_interrupt_no_ack,
3546 + .suspend = genphy_suspend,
3547 + .resume = genphy_resume,
3548 + .read_page = mtk_gephy_read_page,
3549 + .write_page = mtk_gephy_write_page,
3550 + },
3551 +};
3552 +
3553 +module_phy_driver(mtk_gephy_driver);
3554 +
3555 +static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
3556 + { PHY_ID_MATCH_EXACT(0x03a29441) },
3557 + { PHY_ID_MATCH_EXACT(0x03a29412) },
3558 + { }
3559 +};
3560 +
3561 +MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver");
3562 +MODULE_AUTHOR("DENG, Qingfang <dqfext@gmail.com>");
3563 +MODULE_LICENSE("GPL");
3564 +
3565 +MODULE_DEVICE_TABLE(mdio, mtk_gephy_tbl);
Mirror of https://github.com/openwrt/openwrt.git