git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From 3e4b53e04281ed3d9c7a4329c027097265c04d54 Mon Sep 17 00:00:00 2001
   2 From: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
   3 Date: Mon, 25 Sep 2023 15:58:26 +0530
   4 Subject: [PATCH] arm64: dts: qcom: ipq5018: enable the CPUFreq support
   5
   6 Add the APCS, A53 PLL, cpu-opp-table nodes to set
   7 the CPU frequency at 800MHz (idle) or 1.008GHz.
   8
   9 Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
  10 Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
  11 Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
  12 Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  13 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  14 Link: https://lore.kernel.org/r/20230925102826.405446-4-quic_gokulsri@quicinc.com
  15 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  16 ---
  17  arch/arm64/boot/dts/qcom/ipq5018.dtsi | 40 +++++++++++++++++++++++++++
  18  1 file changed, 40 insertions(+)
  19
  20 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
  21 +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
  22 @@ -5,6 +5,7 @@
  23   * Copyright (c) 2023 The Linux Foundation. All rights reserved.
  24   */
  25
  26 +#include <dt-bindings/clock/qcom,apss-ipq.h>
  27  #include <dt-bindings/interrupt-controller/arm-gic.h>
  28  #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
  29  #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
  30 @@ -36,6 +37,8 @@
  31                         reg = <0x0>;
  32                         enable-method = "psci";
  33                         next-level-cache = <&L2_0>;
  34 +                       clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  35 +                       operating-points-v2 = <&cpu_opp_table>;
  36                 };
  37
  38                 CPU1: cpu@1 {
  39 @@ -44,6 +47,8 @@
  40                         reg = <0x1>;
  41                         enable-method = "psci";
  42                         next-level-cache = <&L2_0>;
  43 +                       clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  44 +                       operating-points-v2 = <&cpu_opp_table>;
  45                 };
  46
  47                 L2_0: l2-cache {
  48 @@ -54,6 +59,25 @@
  49                 };
  50         };
  51
  52 +       cpu_opp_table: opp-table-cpu {
  53 +               compatible = "operating-points-v2";
  54 +               opp-shared;
  55 +
  56 +               /*
  57 +               opp-800000000 {
  58 +                       opp-hz = /bits/ 64 <800000000>;
  59 +                       opp-microvolt = <1100000>;
  60 +                       clock-latency-ns = <200000>;
  61 +               };
  62 +               */
  63 +
  64 +               opp-1008000000 {
  65 +                       opp-hz = /bits/ 64 <1008000000>;
  66 +                       opp-microvolt = <1100000>;
  67 +                       clock-latency-ns = <200000>;
  68 +               };
  69 +       };
  70 +
  71         firmware {
  72                 scm {
  73                         compatible = "qcom,scm-ipq5018", "qcom,scm";
  74 @@ -267,6 +291,24 @@
  75                         clocks = <&sleep_clk>;
  76                 };
  77
  78 +               apcs_glb: mailbox@b111000 {
  79 +                       compatible = "qcom,ipq5018-apcs-apps-global",
  80 +                                    "qcom,ipq6018-apcs-apps-global";
  81 +                       reg = <0x0b111000 0x1000>;
  82 +                       #clock-cells = <1>;
  83 +                       clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>;
  84 +                       clock-names = "pll", "xo", "gpll0";
  85 +                       #mbox-cells = <1>;
  86 +               };
  87 +
  88 +               a53pll: clock@b116000 {
  89 +                       compatible = "qcom,ipq5018-a53pll";
  90 +                       reg = <0x0b116000 0x40>;
  91 +                       #clock-cells = <0>;
  92 +                       clocks = <&xo_board_clk>;
  93 +                       clock-names = "xo";
  94 +               };
  95 +
  96                 timer@b120000 {
  97                         compatible = "arm,armv7-timer-mem";
  98                         reg = <0x0b120000 0x1000>;