git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From 2f2f5ae4d52ea882ba58f6b2fa6373a3d3db2bce Mon Sep 17 00:00:00 2001
   2 From: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
   3 Date: Thu, 13 Mar 2025 12:44:22 +0530
   4 Subject: [PATCH] arm64: dts: qcom: ipq9574: fix the msi interrupt numbers of
   5  pcie3
   6
   7 The MSI interrupt numbers of the PCIe3 controller are incorrect. Due
   8 to this, the functional bring up of the QDSP6 processor on the PCIe
   9 endpoint has failed. Correct the MSI interrupt numbers to properly
  10 bring up the QDSP6 processor on the PCIe endpoint.
  11
  12 Fixes: d80c7fbfa908 ("arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes")
  13 Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
  14 Link: https://lore.kernel.org/r/20250313071422.510-1-quic_mmanikan@quicinc.com
  15 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  16 ---
  17  arch/arm64/boot/dts/qcom/ipq9574.dtsi | 16 ++++++++--------
  18  1 file changed, 8 insertions(+), 8 deletions(-)
  19
  20 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
  21 +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
  22 @@ -972,14 +972,14 @@
  23                         ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>,
  24                                  <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>;
  25
  26 -                       interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
  27 -                                    <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
  28 -                                    <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
  29 -                                    <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
  30 -                                    <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  31 -                                    <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
  32 -                                    <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
  33 -                                    <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
  34 +                       interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
  35 +                                    <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
  36 +                                    <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
  37 +                                    <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
  38 +                                    <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
  39 +                                    <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
  40 +                                    <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
  41 +                                    <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>;
  42                         interrupt-names = "msi0",
  43                                           "msi1",
  44                                           "msi2",