git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From 33f393a2a990e16f56931ca708295f31d2b44415 Mon Sep 17 00:00:00 2001
   2 From: Sebastian Reichel <sebastian.reichel@collabora.com>
   3 Date: Tue, 9 Apr 2024 00:50:34 +0200
   4 Subject: [PATCH] arm64: dts: rockchip: add USB3 DRD controllers on rk3588
   5
   6 Add both USB3 dual-role controllers to the RK3588 devicetree.
   7
   8 Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
   9 Link: https://lore.kernel.org/r/20240408225109.128953-8-sebastian.reichel@collabora.com
  10 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  11 ---
  12  arch/arm64/boot/dts/rockchip/rk3588.dtsi  | 20 ++++++++++++++++++++
  13  arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 22 ++++++++++++++++++++++
  14  2 files changed, 42 insertions(+)
  15
  16 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
  17 +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
  18 @@ -7,6 +7,26 @@
  19  #include "rk3588-pinctrl.dtsi"
  20
  21  / {
  22 +       usb_host1_xhci: usb@fc400000 {
  23 +               compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
  24 +               reg = <0x0 0xfc400000 0x0 0x400000>;
  25 +               interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
  26 +               clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
  27 +                        <&cru ACLK_USB3OTG1>;
  28 +               clock-names = "ref_clk", "suspend_clk", "bus_clk";
  29 +               dr_mode = "otg";
  30 +               phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
  31 +               phy-names = "usb2-phy", "usb3-phy";
  32 +               phy_type = "utmi_wide";
  33 +               power-domains = <&power RK3588_PD_USB>;
  34 +               resets = <&cru SRST_A_USB3OTG1>;
  35 +               snps,dis_enblslpm_quirk;
  36 +               snps,dis-u2-freeclk-exists-quirk;
  37 +               snps,dis-del-phy-power-chg-quirk;
  38 +               snps,dis-tx-ipgap-linecheck-quirk;
  39 +               status = "disabled";
  40 +       };
  41 +
  42         pcie30_phy_grf: syscon@fd5b8000 {
  43                 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
  44                 reg = <0x0 0xfd5b8000 0x0 0x10000>;
  45 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
  46 +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
  47 @@ -492,6 +492,28 @@
  48                 };
  49         };
  50
  51 +       usb_host0_xhci: usb@fc000000 {
  52 +               compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
  53 +               reg = <0x0 0xfc000000 0x0 0x400000>;
  54 +               interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
  55 +               clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
  56 +                        <&cru ACLK_USB3OTG0>;
  57 +               clock-names = "ref_clk", "suspend_clk", "bus_clk";
  58 +               dr_mode = "otg";
  59 +               phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
  60 +               phy-names = "usb2-phy", "usb3-phy";
  61 +               phy_type = "utmi_wide";
  62 +               power-domains = <&power RK3588_PD_USB>;
  63 +               resets = <&cru SRST_A_USB3OTG0>;
  64 +               snps,dis_enblslpm_quirk;
  65 +               snps,dis-u1-entry-quirk;
  66 +               snps,dis-u2-entry-quirk;
  67 +               snps,dis-u2-freeclk-exists-quirk;
  68 +               snps,dis-del-phy-power-chg-quirk;
  69 +               snps,dis-tx-ipgap-linecheck-quirk;
  70 +               status = "disabled";
  71 +       };
  72 +
  73         usb_host0_ehci: usb@fc800000 {
  74                 compatible = "rockchip,rk3588-ehci", "generic-ehci";
  75                 reg = <0x0 0xfc800000 0x0 0x40000>;