git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From 9a108c82b6f6526e0aa8a19befa1ed3f31f8fe52 Mon Sep 17 00:00:00 2001
   2 From: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
   3 Date: Fri, 10 May 2024 15:42:29 +0100
   4 Subject: [PATCH 1178/1215] dts: rp1: DSI drivers to use newly defined MIPI
   5  byte source clocks.
   6
   7 Remove the "dummy" 72MHz fixed clock sources and associate DSI driver
   8 with the new "variable" clock sources now defined in RP1 clocks.
   9
  10 Also add PLLSYS clock to DSI, which it will need as an alternative
  11 clock source in those cases where DPI pixclock > DSI byteclock.
  12
  13 Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
  14 ---
  15  arch/arm/boot/dts/broadcom/rp1.dtsi | 50 +++++++++--------------------
  16  1 file changed, 15 insertions(+), 35 deletions(-)
  17
  18 --- a/arch/arm/boot/dts/broadcom/rp1.dtsi
  19 +++ b/arch/arm/boot/dts/broadcom/rp1.dtsi
  20 @@ -1109,16 +1109,15 @@
  21
  22                         interrupts = <RP1_INT_MIPI0 IRQ_TYPE_LEVEL_HIGH>;
  23
  24 -                       clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>,  // required, config bus clock
  25 -                                <&rp1_clocks RP1_CLK_MIPI0_DPI>,  // required, pixel clock
  26 -                                <&clksrc_mipi0_dsi_byteclk>,    // internal, parent for divide
  27 -                                <&clk_xosc>;                    // hardwired to DSI "refclk"
  28 -                       clock-names = "cfgclk", "dpiclk", "byteclk", "refclk";
  29 +                       clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>,
  30 +                                <&rp1_clocks RP1_CLK_MIPI0_DPI>,
  31 +                                <&rp1_clocks RP1_CLK_MIPI0_DSI_BYTECLOCK>,
  32 +                                <&clk_xosc>,                // hardwired to DSI "refclk"
  33 +                                <&rp1_clocks RP1_PLL_SYS>;  // alternate parent for divide
  34 +                       clock-names = "cfgclk", "dpiclk", "byteclk", "refclk", "pllsys";
  35
  36 -                       assigned-clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>,
  37 -                                         <&rp1_clocks RP1_CLK_MIPI0_DPI>;
  38 +                       assigned-clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>;
  39                         assigned-clock-rates = <25000000>;
  40 -                       assigned-clock-parents = <0>, <&clksrc_mipi0_dsi_byteclk>;
  41                 };
  42
  43                 rp1_dsi1: dsi@128000 {
  44 @@ -1130,16 +1129,15 @@
  45
  46                         interrupts = <RP1_INT_MIPI1 IRQ_TYPE_LEVEL_HIGH>;
  47
  48 -                       clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>,  // required, config bus clock
  49 -                                <&rp1_clocks RP1_CLK_MIPI1_DPI>,  // required, pixel clock
  50 -                                <&clksrc_mipi1_dsi_byteclk>,    // internal, parent for divide
  51 -                                <&clk_xosc>;                    // hardwired to DSI "refclk"
  52 -                       clock-names = "cfgclk", "dpiclk", "byteclk", "refclk";
  53 +                       clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>,
  54 +                                <&rp1_clocks RP1_CLK_MIPI1_DPI>,
  55 +                                <&rp1_clocks RP1_CLK_MIPI1_DSI_BYTECLOCK>,
  56 +                                <&clk_xosc>,               // hardwired to DSI "refclk"
  57 +                                <&rp1_clocks RP1_PLL_SYS>; // alternate parent for divide
  58 +                       clock-names = "cfgclk", "dpiclk", "byteclk", "refclk", "pllsys";
  59
  60 -                       assigned-clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>,
  61 -                                         <&rp1_clocks RP1_CLK_MIPI1_DPI>;
  62 +                       assigned-clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>;
  63                         assigned-clock-rates = <25000000>;
  64 -                       assigned-clock-parents = <0>, <&clksrc_mipi1_dsi_byteclk>;
  65                 };
  66
  67                 /* VEC and DPI both need to control PLL_VIDEO and cannot work together;   */
  68 @@ -1216,24 +1214,6 @@
  69                 clock-output-names = "core";
  70                 clock-frequency = <50000000>;
  71         };
  72 -       clksrc_mipi0_dsi_byteclk: clksrc_mipi0_dsi_byteclk {
  73 -               // This clock is synthesized by MIPI0 D-PHY, when DSI is running.
  74 -               // Its frequency is not known a priori (until a panel driver attaches)
  75 -               // so assign a made-up frequency of 72MHz so it can be divided for DPI.
  76 -               compatible = "fixed-clock";
  77 -               #clock-cells = <0>;
  78 -               clock-output-names = "clksrc_mipi0_dsi_byteclk";
  79 -               clock-frequency = <72000000>;
  80 -       };
  81 -       clksrc_mipi1_dsi_byteclk: clksrc_mipi1_dsi_byteclk {
  82 -               // This clock is synthesized by MIPI1 D-PHY, when DSI is running.
  83 -               // Its frequency is not known a priori (until a panel driver attaches)
  84 -               // so assign a made-up frequency of 72MHz so it can be divided for DPI.
  85 -               compatible = "fixed-clock";
  86 -               #clock-cells = <0>;
  87 -               clock-output-names = "clksrc_mipi1_dsi_byteclk";
  88 -               clock-frequency = <72000000>;
  89 -       };
  90         /* GPIO derived clock sources. Each GPIO with a GPCLK function
  91          * can drive its output from the respective GPCLK
  92          * generator, and provide a clock source to other internal