1 From abe68e0ca71dddce0e5419e35507cb464d61870d Mon Sep 17 00:00:00 2001
2 From: Sebastian Reichel <sebastian.reichel@collabora.com>
3 Date: Tue, 9 Apr 2024 00:50:32 +0200
4 Subject: [PATCH] arm64: dts: rockchip: reorder usb2phy properties for rk3588
6 Reorder common DT properties alphabetically for usb2phy, according
7 to latest DT style rules.
9 Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
10 Link: https://lore.kernel.org/r/20240408225109.128953-6-sebastian.reichel@collabora.com
11 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
13 arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 ++++++++--------
14 1 file changed, 8 insertions(+), 8 deletions(-)
16 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
17 +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
19 u2phy2: usb2phy@8000 {
20 compatible = "rockchip,rk3588-usb2phy";
22 - interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
23 - resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
24 - reset-names = "phy", "apb";
26 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
27 clock-names = "phyclk";
28 clock-output-names = "usb480m_phy2";
30 + interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
31 + resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
32 + reset-names = "phy", "apb";
35 u2phy2_host: host-port {
37 u2phy3: usb2phy@c000 {
38 compatible = "rockchip,rk3588-usb2phy";
40 - interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
41 - resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
42 - reset-names = "phy", "apb";
44 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
45 clock-names = "phyclk";
46 clock-output-names = "usb480m_phy3";
48 + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
49 + resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
50 + reset-names = "phy", "apb";
53 u2phy3_host: host-port {