git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From d06b1043644a1831ab141bbee2669002bba15b0f Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Wed, 20 Dec 2023 23:17:22 +0100
   4 Subject: [PATCH 1/2] clk: qcom: clk-rcg: introduce support for multiple conf
   5  for same freq
   6
   7 Some RCG frequency can be reached by multiple configuration.
   8
   9 We currently declare multiple configuration for the same frequency but
  10 that is not supported and always the first configuration will be taken.
  11
  12 These multiple configuration are needed as based on the current parent
  13 configuration, it may be needed to use a different configuration to
  14 reach the same frequency.
  15
  16 To handle this introduce 3 new macro, C, FM and FMS:
  17
  18 - C is used to declare a freq_conf where src, pre_div, m and n are
  19   provided.
  20
  21 - FM is used to declare a freq_multi_tbl with the frequency and an
  22   array of confs to insert all the config for the provided frequency.
  23
  24 - FMS is used to declare a freq_multi_tbl with the frequency and an
  25   array of a single conf with the provided src, pre_div, m and n.
  26
  27 Struct clk_rcg2 is changed to add a union type to reference a simple
  28 freq_tbl or a complex freq_multi_tbl.
  29
  30 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  31 Acked-by: Stephen Boyd <sboyd@kernel.org>
  32 Link: https://lore.kernel.org/r/20231220221724.3822-2-ansuelsmth@gmail.com
  33 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  34 ---
  35  drivers/clk/qcom/clk-rcg.h | 23 ++++++++++++++++++++++-
  36  1 file changed, 22 insertions(+), 1 deletion(-)
  37
  38 --- a/drivers/clk/qcom/clk-rcg.h
  39 +++ b/drivers/clk/qcom/clk-rcg.h
  40 @@ -17,6 +17,23 @@ struct freq_tbl {
  41         u16 n;
  42  };
  43
  44 +#define C(s, h, m, n) { (s), (2 * (h) - 1), (m), (n) }
  45 +#define FM(f, confs) { (f), ARRAY_SIZE(confs), (confs) }
  46 +#define FMS(f, s, h, m, n) { (f), 1, (const struct freq_conf []){ C(s, h, m, n) } }
  47 +
  48 +struct freq_conf {
  49 +       u8 src;
  50 +       u8 pre_div;
  51 +       u16 m;
  52 +       u16 n;
  53 +};
  54 +
  55 +struct freq_multi_tbl {
  56 +       unsigned long freq;
  57 +       size_t num_confs;
  58 +       const struct freq_conf *confs;
  59 +};
  60 +
  61  /**
  62   * struct mn - M/N:D counter
  63   * @mnctr_en_bit: bit to enable mn counter
  64 @@ -138,6 +155,7 @@ extern const struct clk_ops clk_dyn_rcg_
  65   * @safe_src_index: safe src index value
  66   * @parent_map: map from software's parent index to hardware's src_sel field
  67   * @freq_tbl: frequency table
  68 + * @freq_multi_tbl: frequency table for clocks reachable with multiple RCGs conf
  69   * @clkr: regmap clock handle
  70   * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG
  71   * @parked_cfg: cached value of the CFG register for parked RCGs
  72 @@ -149,7 +167,10 @@ struct clk_rcg2 {
  73         u8                      hid_width;
  74         u8                      safe_src_index;
  75         const struct parent_map *parent_map;
  76 -       const struct freq_tbl   *freq_tbl;
  77 +       union {
  78 +               const struct freq_tbl           *freq_tbl;
  79 +               const struct freq_multi_tbl     *freq_multi_tbl;
  80 +       };
  81         struct clk_regmap       clkr;
  82         u8                      cfg_off;
  83         u32                     parked_cfg;