]> git.ipfire.org Git - thirdparty/openwrt.git/blob
projects / thirdparty / openwrt.git / blob
? search:


91fc8082e923f658d9d88fc74c9e2ceb75a178b4
[thirdparty/openwrt.git] /
1 From c9ad8286ca39c2545f6a6851a8ede8488a9263f3 Mon Sep 17 00:00:00 2001
2 From: Pavithra R <quic_pavir@quicinc.com>
3 Date: Tue, 11 Jun 2024 00:00:46 +0530
4 Subject: [PATCH 44/50] net: ethernet: qualcomm: Add module parameters for
5 driver tunings
6
7 Add module params and corresponding functionality for Tx/Rx
8 mitigation timer/packet count, napi budget and tx requeue stop.
9
10 Change-Id: I1717559c931bba4f355ee06ab89f289818400ca2
11 Signed-off-by: Pavithra R <quic_pavir@quicinc.com>
12 ---
13 drivers/net/ethernet/qualcomm/ppe/edma.c | 35 +++++++++++++++++++
14 .../net/ethernet/qualcomm/ppe/edma_cfg_rx.c | 29 +++++++++++++--
15 .../net/ethernet/qualcomm/ppe/edma_cfg_rx.h | 21 +++++++++++
16 .../net/ethernet/qualcomm/ppe/edma_cfg_tx.c | 29 +++++++++++++--
17 .../net/ethernet/qualcomm/ppe/edma_cfg_tx.h | 16 +++++++++
18 drivers/net/ethernet/qualcomm/ppe/edma_rx.h | 4 +++
19 drivers/net/ethernet/qualcomm/ppe/edma_tx.h | 4 +++
20 7 files changed, 134 insertions(+), 4 deletions(-)
21
22 --- a/drivers/net/ethernet/qualcomm/ppe/edma.c
23 +++ b/drivers/net/ethernet/qualcomm/ppe/edma.c
24 @@ -38,6 +38,38 @@ static int rx_buff_size;
25 module_param(rx_buff_size, int, 0640);
26 MODULE_PARM_DESC(rx_buff_size, "Rx Buffer size for Jumbo MRU value (default:0)");
27
28 +int edma_rx_napi_budget = EDMA_RX_NAPI_WORK_DEF;
29 +module_param(edma_rx_napi_budget, int, 0444);
30 +MODULE_PARM_DESC(edma_rx_napi_budget, "Rx NAPI budget (default:128, min:16, max:512)");
31 +
32 +int edma_tx_napi_budget = EDMA_TX_NAPI_WORK_DEF;
33 +module_param(edma_tx_napi_budget, int, 0444);
34 +MODULE_PARM_DESC(edma_tx_napi_budget, "Tx NAPI budget (default:512 for ipq95xx, min:16, max:512)");
35 +
36 +int edma_rx_mitigation_pkt_cnt = EDMA_RX_MITIGATION_PKT_CNT_DEF;
37 +module_param(edma_rx_mitigation_pkt_cnt, int, 0444);
38 +MODULE_PARM_DESC(edma_rx_mitigation_pkt_cnt,
39 + "Rx mitigation packet count value (default:16, min:0, max: 256)");
40 +
41 +s32 edma_rx_mitigation_timer = EDMA_RX_MITIGATION_TIMER_DEF;
42 +module_param(edma_rx_mitigation_timer, int, 0444);
43 +MODULE_PARM_DESC(edma_dp_rx_mitigation_timer,
44 + "Rx mitigation timer value in microseconds (default:25, min:0, max: 1000)");
45 +
46 +int edma_tx_mitigation_timer = EDMA_TX_MITIGATION_TIMER_DEF;
47 +module_param(edma_tx_mitigation_timer, int, 0444);
48 +MODULE_PARM_DESC(edma_tx_mitigation_timer,
49 + "Tx mitigation timer value in microseconds (default:250, min:0, max: 1000)");
50 +
51 +int edma_tx_mitigation_pkt_cnt = EDMA_TX_MITIGATION_PKT_CNT_DEF;
52 +module_param(edma_tx_mitigation_pkt_cnt, int, 0444);
53 +MODULE_PARM_DESC(edma_tx_mitigation_pkt_cnt,
54 + "Tx mitigation packet count value (default:16, min:0, max: 256)");
55 +
56 +static int tx_requeue_stop;
57 +module_param(tx_requeue_stop, int, 0640);
58 +MODULE_PARM_DESC(tx_requeue_stop, "Disable Tx requeue function (default:0)");
59 +
60 /* Priority to multi-queue mapping. */
61 static u8 edma_pri_map[PPE_QUEUE_INTER_PRI_NUM] = {
62 0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7};
63 @@ -828,7 +860,10 @@ int edma_setup(struct ppe_device *ppe_de
64 edma_ctx->hw_info = &ipq9574_hw_info;
65 edma_ctx->ppe_dev = ppe_dev;
66 edma_ctx->rx_buf_size = rx_buff_size;
67 +
68 edma_ctx->tx_requeue_stop = false;
69 + if (tx_requeue_stop != 0)
70 + edma_ctx->tx_requeue_stop = true;
71
72 /* Configure the EDMA common clocks. */
73 ret = edma_clock_init();
74 --- a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.c
75 +++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.c
76 @@ -166,6 +166,24 @@ static void edma_cfg_rx_desc_ring_config
77 reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_RING_SIZE(rxdesc_ring->ring_id);
78 regmap_write(regmap, reg, data);
79
80 + /* Validate mitigation timer value */
81 + if (edma_rx_mitigation_timer < EDMA_RX_MITIGATION_TIMER_MIN ||
82 + edma_rx_mitigation_timer > EDMA_RX_MITIGATION_TIMER_MAX) {
83 + pr_err("Invalid Rx mitigation timer configured:%d for ring:%d. Using the default timer value:%d\n",
84 + edma_rx_mitigation_timer, rxdesc_ring->ring_id,
85 + EDMA_RX_MITIGATION_TIMER_DEF);
86 + edma_rx_mitigation_timer = EDMA_RX_MITIGATION_TIMER_DEF;
87 + }
88 +
89 + /* Validate mitigation packet count value */
90 + if (edma_rx_mitigation_pkt_cnt < EDMA_RX_MITIGATION_PKT_CNT_MIN ||
91 + edma_rx_mitigation_pkt_cnt > EDMA_RX_MITIGATION_PKT_CNT_MAX) {
92 + pr_err("Invalid Rx mitigation packet count configured:%d for ring:%d. Using the default packet counter value:%d\n",
93 + edma_rx_mitigation_timer, rxdesc_ring->ring_id,
94 + EDMA_RX_MITIGATION_PKT_CNT_DEF);
95 + edma_rx_mitigation_pkt_cnt = EDMA_RX_MITIGATION_PKT_CNT_DEF;
96 + }
97 +
98 /* Configure the Mitigation timer */
99 data = EDMA_MICROSEC_TO_TIMER_UNIT(EDMA_RX_MITIGATION_TIMER_DEF,
100 ppe_dev->clk_rate / MHZ);
101 @@ -176,7 +194,7 @@ static void edma_cfg_rx_desc_ring_config
102 regmap_write(regmap, reg, data);
103
104 /* Configure the Mitigation packet count */
105 - data = (EDMA_RX_MITIGATION_PKT_CNT_DEF & EDMA_RXDESC_LOW_THRE_MASK)
106 + data = (edma_rx_mitigation_pkt_cnt & EDMA_RXDESC_LOW_THRE_MASK)
107 << EDMA_RXDESC_LOW_THRE_SHIFT;
108 pr_debug("EDMA Rx mitigation packet count value: %d\n", data);
109 reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_UGT_THRE(rxdesc_ring->ring_id);
110 @@ -915,6 +933,13 @@ void edma_cfg_rx_napi_add(void)
111 struct edma_ring_info *rx = hw_info->rx;
112 u32 i;
113
114 + if (edma_rx_napi_budget < EDMA_RX_NAPI_WORK_MIN ||
115 + edma_rx_napi_budget > EDMA_RX_NAPI_WORK_MAX) {
116 + pr_err("Incorrect Rx NAPI budget: %d, setting to default: %d",
117 + edma_rx_napi_budget, hw_info->napi_budget_rx);
118 + edma_rx_napi_budget = hw_info->napi_budget_rx;
119 + }
120 +
121 for (i = 0; i < rx->num_rings; i++) {
122 struct edma_rxdesc_ring *rxdesc_ring = &edma_ctx->rx_rings[i];
123
124 @@ -923,7 +948,7 @@ void edma_cfg_rx_napi_add(void)
125 rxdesc_ring->napi_added = true;
126 }
127
128 - netdev_dbg(edma_ctx->dummy_dev, "Rx NAPI budget: %d\n", hw_info->napi_budget_rx);
129 + netdev_dbg(edma_ctx->dummy_dev, "Rx NAPI budget: %d\n", edma_rx_napi_budget);
130 }
131
132 /**
133 --- a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.h
134 +++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.h
135 @@ -5,6 +5,15 @@
136 #ifndef __EDMA_CFG_RX__
137 #define __EDMA_CFG_RX__
138
139 +/* Rx default NAPI budget */
140 +#define EDMA_RX_NAPI_WORK_DEF 128
141 +
142 +/* RX minimum NAPI budget */
143 +#define EDMA_RX_NAPI_WORK_MIN 16
144 +
145 +/* Rx maximum NAPI budget */
146 +#define EDMA_RX_NAPI_WORK_MAX 512
147 +
148 /* SKB payload size used in page mode */
149 #define EDMA_RX_PAGE_MODE_SKB_SIZE 256
150
151 @@ -22,9 +31,21 @@
152 /* Rx mitigation timer's default value in microseconds */
153 #define EDMA_RX_MITIGATION_TIMER_DEF 25
154
155 +/* Rx mitigation timer's minimum value in microseconds */
156 +#define EDMA_RX_MITIGATION_TIMER_MIN 0
157 +
158 +/* Rx mitigation timer's maximum value in microseconds */
159 +#define EDMA_RX_MITIGATION_TIMER_MAX 1000
160 +
161 /* Rx mitigation packet count's default value */
162 #define EDMA_RX_MITIGATION_PKT_CNT_DEF 16
163
164 +/* Rx mitigation packet count's minimum value */
165 +#define EDMA_RX_MITIGATION_PKT_CNT_MIN 0
166 +
167 +/* Rx mitigation packet count's maximum value */
168 +#define EDMA_RX_MITIGATION_PKT_CNT_MAX 256
169 +
170 /* Default bitmap of cores for RPS to ARM cores */
171 #define EDMA_RX_DEFAULT_BITMAP ((1 << EDMA_MAX_CORE) - 1)
172
173 --- a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.c
174 +++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.c
175 @@ -170,6 +170,24 @@ static void edma_cfg_txcmpl_ring_configu
176 reg = EDMA_BASE_OFFSET + EDMA_REG_TXCMPL_CTRL(txcmpl_ring->id);
177 regmap_write(regmap, reg, EDMA_TXCMPL_RETMODE_OPAQUE);
178
179 + /* Validate mitigation timer value */
180 + if (edma_tx_mitigation_timer < EDMA_TX_MITIGATION_TIMER_MIN ||
181 + edma_tx_mitigation_timer > EDMA_TX_MITIGATION_TIMER_MAX) {
182 + pr_err("Invalid Tx mitigation timer configured:%d for ring:%d. Using the default timer value:%d\n",
183 + edma_tx_mitigation_timer, txcmpl_ring->id,
184 + EDMA_TX_MITIGATION_TIMER_DEF);
185 + edma_tx_mitigation_timer = EDMA_TX_MITIGATION_TIMER_DEF;
186 + }
187 +
188 + /* Validate mitigation packet count value */
189 + if (edma_tx_mitigation_pkt_cnt < EDMA_TX_MITIGATION_PKT_CNT_MIN ||
190 + edma_tx_mitigation_pkt_cnt > EDMA_TX_MITIGATION_PKT_CNT_MAX) {
191 + pr_err("Invalid Tx mitigation packet count configured:%d for ring:%d. Using the default packet counter value:%d\n",
192 + edma_tx_mitigation_timer, txcmpl_ring->id,
193 + EDMA_TX_MITIGATION_PKT_CNT_DEF);
194 + edma_tx_mitigation_pkt_cnt = EDMA_TX_MITIGATION_PKT_CNT_DEF;
195 + }
196 +
197 /* Configure the Mitigation timer. */
198 data = EDMA_MICROSEC_TO_TIMER_UNIT(EDMA_TX_MITIGATION_TIMER_DEF,
199 ppe_dev->clk_rate / MHZ);
200 @@ -180,7 +198,7 @@ static void edma_cfg_txcmpl_ring_configu
201 regmap_write(regmap, reg, data);
202
203 /* Configure the Mitigation packet count. */
204 - data = (EDMA_TX_MITIGATION_PKT_CNT_DEF & EDMA_TXCMPL_LOW_THRE_MASK)
205 + data = (edma_tx_mitigation_pkt_cnt & EDMA_TXCMPL_LOW_THRE_MASK)
206 << EDMA_TXCMPL_LOW_THRE_SHIFT;
207 pr_debug("EDMA Tx mitigation packet count value: %d\n", data);
208 reg = EDMA_BASE_OFFSET + EDMA_REG_TXCMPL_UGT_THRE(txcmpl_ring->id);
209 @@ -634,6 +652,13 @@ void edma_cfg_tx_napi_add(struct net_dev
210 struct edma_txcmpl_ring *txcmpl_ring;
211 u32 i, ring_idx;
212
213 + if (edma_tx_napi_budget < EDMA_TX_NAPI_WORK_MIN ||
214 + edma_tx_napi_budget > EDMA_TX_NAPI_WORK_MAX) {
215 + pr_err("Incorrect Tx NAPI budget: %d, setting to default: %d",
216 + edma_tx_napi_budget, hw_info->napi_budget_tx);
217 + edma_tx_napi_budget = hw_info->napi_budget_tx;
218 + }
219 +
220 /* Adding tx napi for a interface with each queue. */
221 for_each_possible_cpu(i) {
222 ring_idx = ((port_id - 1) * num_possible_cpus()) + i;
223 @@ -644,5 +669,5 @@ void edma_cfg_tx_napi_add(struct net_dev
224 netdev_dbg(netdev, "Napi added for txcmpl ring: %u\n", txcmpl_ring->id);
225 }
226
227 - netdev_dbg(netdev, "Tx NAPI budget: %d\n", hw_info->napi_budget_tx);
228 + netdev_dbg(netdev, "Tx NAPI budget: %d\n", edma_tx_napi_budget);
229 }
230 --- a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.h
231 +++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.h
232 @@ -5,12 +5,28 @@
233 #ifndef __EDMA_CFG_TX__
234 #define __EDMA_CFG_TX__
235
236 +#define EDMA_TX_NAPI_WORK_DEF 512
237 +#define EDMA_TX_NAPI_WORK_MIN 16
238 +#define EDMA_TX_NAPI_WORK_MAX 512
239 +
240 /* Tx mitigation timer's default value. */
241 #define EDMA_TX_MITIGATION_TIMER_DEF 250
242
243 +/* Tx mitigation timer's minimum value in microseconds */
244 +#define EDMA_TX_MITIGATION_TIMER_MIN 0
245 +
246 +/* Tx mitigation timer's maximum value in microseconds */
247 +#define EDMA_TX_MITIGATION_TIMER_MAX 1000
248 +
249 /* Tx mitigation packet count default value. */
250 #define EDMA_TX_MITIGATION_PKT_CNT_DEF 16
251
252 +/* Tx mitigation packet count's minimum value */
253 +#define EDMA_TX_MITIGATION_PKT_CNT_MIN 0
254 +
255 +/* Tx mitigation packet count's maximum value */
256 +#define EDMA_TX_MITIGATION_PKT_CNT_MAX 256
257 +
258 void edma_cfg_tx_rings(void);
259 int edma_cfg_tx_rings_alloc(void);
260 void edma_cfg_tx_rings_cleanup(void);
261 --- a/drivers/net/ethernet/qualcomm/ppe/edma_rx.h
262 +++ b/drivers/net/ethernet/qualcomm/ppe/edma_rx.h
263 @@ -281,6 +281,10 @@ struct edma_rxdesc_ring {
264 struct sk_buff *last;
265 };
266
267 +extern int edma_rx_napi_budget;
268 +extern int edma_rx_mitigation_timer;
269 +extern int edma_rx_mitigation_pkt_cnt;
270 +
271 irqreturn_t edma_rx_handle_irq(int irq, void *ctx);
272 int edma_rx_alloc_buffer(struct edma_rxfill_ring *rxfill_ring, int alloc_count);
273 int edma_rx_napi_poll(struct napi_struct *napi, int budget);
274 --- a/drivers/net/ethernet/qualcomm/ppe/edma_tx.h
275 +++ b/drivers/net/ethernet/qualcomm/ppe/edma_tx.h
276 @@ -288,6 +288,10 @@ struct edma_txcmpl_ring {
277 bool napi_added;
278 };
279
280 +extern int edma_tx_napi_budget;
281 +extern int edma_tx_mitigation_timer;
282 +extern int edma_tx_mitigation_pkt_cnt;
283 +
284 enum edma_tx_status edma_tx_ring_xmit(struct net_device *netdev,
285 struct sk_buff *skb,
286 struct edma_txdesc_ring *txdesc_ring,
Mirror of https://github.com/openwrt/openwrt.git