git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From b36074357baf2794c825ea1c145de1d22b15380b Mon Sep 17 00:00:00 2001
   2 From: Varadarajan Narayanan <quic_varada@quicinc.com>
   3 Date: Fri, 20 Oct 2023 11:49:39 +0530
   4 Subject: [PATCH] arm64: dts: qcom: ipq9574: populate the opp table based on
   5  the eFuse
   6
   7 IPQ95xx SoCs have different OPPs available for the CPU based on
   8 SoC variant. This can be determined from an eFuse register
   9 present in the silicon.
  10
  11 Add support to read the eFuse and populate the OPPs based on it.
  12
  13 Frequency       1.2GHz  1.8GHz  1.5GHz  No      opp-supported-hw
  14                                         Limit
  15 ------------------------------------------------------------
  16 936000000       1       1       1       1       0xf
  17 1104000000      1       1       1       1       0xf
  18 1200000000      1       1       1       1       0xf
  19 1416000000      0       1       1       1       0x7
  20 1488000000      0       1       1       1       0x7
  21 1800000000      0       1       0       1       0x5
  22 2208000000      0       0       0       1       0x1
  23 -----------------------------------------------------------
  24
  25 Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
  26 Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
  27 Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
  28 Link: https://lore.kernel.org/r/14ab08b7cfd904433ca6065fac798d4f221c9d95.1697781921.git.quic_varada@quicinc.com
  29 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  30 ---
  31  arch/arm64/boot/dts/qcom/ipq9574.dtsi | 21 ++++++++++++++++++++-
  32  1 file changed, 20 insertions(+), 1 deletion(-)
  33
  34 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
  35 +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
  36 @@ -107,42 +107,56 @@
  37         };
  38
  39         cpu_opp_table: opp-table-cpu {
  40 -               compatible = "operating-points-v2";
  41 +               compatible = "operating-points-v2-kryo-cpu";
  42                 opp-shared;
  43 +               nvmem-cells = <&cpu_speed_bin>;
  44
  45                 opp-936000000 {
  46                         opp-hz = /bits/ 64 <936000000>;
  47                         opp-microvolt = <725000>;
  48 +                       opp-supported-hw = <0xf>;
  49                         clock-latency-ns = <200000>;
  50                 };
  51
  52                 opp-1104000000 {
  53                         opp-hz = /bits/ 64 <1104000000>;
  54                         opp-microvolt = <787500>;
  55 +                       opp-supported-hw = <0xf>;
  56 +                       clock-latency-ns = <200000>;
  57 +               };
  58 +
  59 +               opp-1200000000 {
  60 +                       opp-hz = /bits/ 64 <1200000000>;
  61 +                       opp-microvolt = <862500>;
  62 +                       opp-supported-hw = <0xf>;
  63                         clock-latency-ns = <200000>;
  64                 };
  65
  66                 opp-1416000000 {
  67                         opp-hz = /bits/ 64 <1416000000>;
  68                         opp-microvolt = <862500>;
  69 +                       opp-supported-hw = <0x7>;
  70                         clock-latency-ns = <200000>;
  71                 };
  72
  73                 opp-1488000000 {
  74                         opp-hz = /bits/ 64 <1488000000>;
  75                         opp-microvolt = <925000>;
  76 +                       opp-supported-hw = <0x7>;
  77                         clock-latency-ns = <200000>;
  78                 };
  79
  80                 opp-1800000000 {
  81                         opp-hz = /bits/ 64 <1800000000>;
  82                         opp-microvolt = <987500>;
  83 +                       opp-supported-hw = <0x5>;
  84                         clock-latency-ns = <200000>;
  85                 };
  86
  87                 opp-2208000000 {
  88                         opp-hz = /bits/ 64 <2208000000>;
  89                         opp-microvolt = <1062500>;
  90 +                       opp-supported-hw = <0x1>;
  91                         clock-latency-ns = <200000>;
  92                 };
  93         };
  94 @@ -234,6 +248,11 @@
  95                         reg = <0x000a4000 0x5a1>;
  96                         #address-cells = <1>;
  97                         #size-cells = <1>;
  98 +
  99 +                       cpu_speed_bin: cpu-speed-bin@15 {
 100 +                               reg = <0x15 0x2>;
 101 +                               bits = <7 2>;
 102 +                       };
 103                 };
 104
 105                 cryptobam: dma-controller@704000 {