]> git.ipfire.org Git - thirdparty/openwrt.git/blob
projects / thirdparty / openwrt.git / blob
? search:


9f05866ae3597e5287de22bf2c909fc2ff7edc51
[thirdparty/openwrt.git] /
1 From 59fda55d75884efea5fc33f6bde55cbc62ab7471 Mon Sep 17 00:00:00 2001
2 From: Stanimir Varbanov <svarbanov@suse.de>
3 Date: Mon, 20 Jan 2025 15:01:11 +0200
4 Subject: [PATCH] irqchip: Add Broadcom bcm2712 MSI-X interrupt controller
5
6 Add an interrupt controller driver for MSI-X Interrupt Peripheral (MIP)
7 hardware block found in bcm2712. The interrupt controller is used to
8 handle MSI-X interrupts from peripherials behind PCIe endpoints like
9 RP1 south bridge found in RPi5.
10
11 There are two MIPs on bcm2712, the first has 64 consecutive SPIs
12 assigned to 64 output vectors, and the second has 17 SPIs, but only
13 8 of them are consecutive starting at the 8th output vector.
14
15 Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
16 ---
17 drivers/irqchip/Kconfig | 14 +-
18 drivers/irqchip/Makefile | 2 +-
19 drivers/irqchip/irq-bcm2712-mip.c | 399 ++++++++++++++----------------
20 3 files changed, 196 insertions(+), 219 deletions(-)
21
22 --- a/drivers/irqchip/Kconfig
23 +++ b/drivers/irqchip/Kconfig
24 @@ -110,12 +110,20 @@ config I8259
25 select IRQ_DOMAIN
26
27 config BCM2712_MIP
28 - bool "Broadcom 2712 MSI-X Interrupt Peripheral support"
29 + tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support"
30 + depends on ARCH_BRCMSTB || COMPILE_TEST
31 + default m if ARCH_BRCMSTB
32 depends on ARM_GIC
33 select GENERIC_IRQ_CHIP
34 - select IRQ_DOMAIN
35 + select IRQ_DOMAIN_HIERARCHY
36 + select GENERIC_MSI_IRQ
37 + select IRQ_MSI_LIB
38 help
39 - Enable support for the Broadcom BCM2712 MSI-X target peripheral.
40 + Enable support for the Broadcom BCM2712 MSI-X target peripheral
41 + (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on
42 + Raspberry Pi 5.
43 +
44 + If unsure say n.
45
46 config BCM6345_L1_IRQ
47 bool
48 --- a/drivers/irqchip/Makefile
49 +++ b/drivers/irqchip/Makefile
50 @@ -62,7 +62,7 @@ obj-$(CONFIG_XTENSA_MX) += irq-xtensa-
51 obj-$(CONFIG_XILINX_INTC) += irq-xilinx-intc.o
52 obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
53 obj-$(CONFIG_SOC_VF610) += irq-vf610-mscm-ir.o
54 -obj-$(CONFIG_BCM2712_MIP) += irq-bcm2712-mip.o
55 +obj-$(CONFIG_BCM2712_MIP) += irq-bcm2712-mip.o
56 obj-$(CONFIG_BCM6345_L1_IRQ) += irq-bcm6345-l1.o
57 obj-$(CONFIG_BCM7038_L1_IRQ) += irq-bcm7038-l1.o
58 obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o
59 --- a/drivers/irqchip/irq-bcm2712-mip.c
60 +++ b/drivers/irqchip/irq-bcm2712-mip.c
61 @@ -1,19 +1,20 @@
62 // SPDX-License-Identifier: GPL-2.0-only
63 /*
64 - * Copyright (C) 2021 Raspberry Pi Ltd., All Rights Reserved.
65 + * Copyright (C) 2024 Raspberry Pi Ltd., All Rights Reserved.
66 + * Copyright (c) 2024 SUSE
67 */
68
69 -#include <linux/pci.h>
70 +#include <linux/bitmap.h>
71 +#include <linux/irqchip.h>
72 +#include <linux/irqdomain.h>
73 #include <linux/msi.h>
74 -#include <linux/of.h>
75 #include <linux/of_address.h>
76 -#include <linux/of_irq.h>
77 -#include <linux/of_pci.h>
78 +#include <linux/of_platform.h>
79
80 -#include <linux/irqchip.h>
81 +#include "irq-msi-lib.h"
82
83 -#define MIP_INT_RAISED 0x00
84 -#define MIP_INT_CLEARED 0x10
85 +#define MIP_INT_RAISE 0x00
86 +#define MIP_INT_CLEAR 0x10
87 #define MIP_INT_CFGL_HOST 0x20
88 #define MIP_INT_CFGH_HOST 0x30
89 #define MIP_INT_MASKL_HOST 0x40
90 @@ -25,57 +26,40 @@
91 #define MIP_INT_STATUSL_VPU 0xa0
92 #define MIP_INT_STATUSH_VPU 0xb0
93
94 +/**
95 + * struct mip_priv - MSI-X interrupt controller data
96 + * @lock: Used to protect bitmap alloc/free
97 + * @base: Base address of MMIO area
98 + * @msg_addr: PCIe MSI-X address
99 + * @msi_base: MSI base
100 + * @num_msis: Count of MSIs
101 + * @msi_offset: MSI offset
102 + * @bitmap: A bitmap for hwirqs
103 + * @parent: Parent domain (GIC)
104 + * @dev: A device pointer
105 + */
106 struct mip_priv {
107 - spinlock_t msi_map_lock;
108 - spinlock_t hw_lock;
109 - void * __iomem base;
110 - phys_addr_t msg_addr;
111 - u32 msi_base; /* The SGI number that MSIs start */
112 - u32 num_msis; /* The number of SGIs for MSIs */
113 - u32 msi_offset; /* Shift the allocated msi up by N */
114 - unsigned long *msi_map;
115 + spinlock_t lock;
116 + void __iomem *base;
117 + u64 msg_addr;
118 + u32 msi_base;
119 + u32 num_msis;
120 + u32 msi_offset;
121 + unsigned long *bitmap;
122 + struct irq_domain *parent;
123 + struct device *dev;
124 };
125
126 -static void mip_mask_msi_irq(struct irq_data *d)
127 -{
128 - pci_msi_mask_irq(d);
129 - irq_chip_mask_parent(d);
130 -}
131 -
132 -static void mip_unmask_msi_irq(struct irq_data *d)
133 -{
134 - pci_msi_unmask_irq(d);
135 - irq_chip_unmask_parent(d);
136 -}
137 -
138 static void mip_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
139 {
140 - struct mip_priv *priv = irq_data_get_irq_chip_data(d);
141 + struct mip_priv *mip = irq_data_get_irq_chip_data(d);
142
143 - msg->address_hi = upper_32_bits(priv->msg_addr);
144 - msg->address_lo = lower_32_bits(priv->msg_addr);
145 + msg->address_hi = upper_32_bits(mip->msg_addr);
146 + msg->address_lo = lower_32_bits(mip->msg_addr);
147 msg->data = d->hwirq;
148 }
149
150 -// The "bus-specific" irq_chip (the MIP doesn't _have_ to be used with PCIe)
151 -
152 -static struct irq_chip mip_msi_irq_chip = {
153 - .name = "MIP-MSI",
154 - .irq_unmask = mip_unmask_msi_irq,
155 - .irq_mask = mip_mask_msi_irq,
156 - .irq_eoi = irq_chip_eoi_parent,
157 - .irq_set_affinity = irq_chip_set_affinity_parent,
158 -};
159 -
160 -static struct msi_domain_info mip_msi_domain_info = {
161 - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
162 - MSI_FLAG_PCI_MSIX),
163 - .chip = &mip_msi_irq_chip,
164 -};
165 -
166 -// The "middle" irq_chip (the hardware control part)
167 -
168 -static struct irq_chip mip_irq_chip = {
169 +static struct irq_chip mip_middle_irq_chip = {
170 .name = "MIP",
171 .irq_mask = irq_chip_mask_parent,
172 .irq_unmask = irq_chip_unmask_parent,
173 @@ -85,239 +69,224 @@ static struct irq_chip mip_irq_chip = {
174 .irq_compose_msi_msg = mip_compose_msi_msg,
175 };
176
177 +static int mip_alloc_hwirq(struct mip_priv *mip, unsigned int nr_irqs)
178 +{
179 + guard(spinlock)(&mip->lock);
180 + return bitmap_find_free_region(mip->bitmap, mip->num_msis, ilog2(nr_irqs));
181 +}
182
183 -// And a domain to connect it to its parent (the GIC)
184 +static void mip_free_hwirq(struct mip_priv *mip, unsigned int hwirq,
185 + unsigned int nr_irqs)
186 +{
187 + guard(spinlock)(&mip->lock);
188 + bitmap_release_region(mip->bitmap, hwirq, ilog2(nr_irqs));
189 +}
190
191 -static int mip_irq_domain_alloc(struct irq_domain *domain,
192 - unsigned int virq, unsigned int nr_irqs,
193 - void *args)
194 +static int mip_middle_domain_alloc(struct irq_domain *domain, unsigned int virq,
195 + unsigned int nr_irqs, void *arg)
196 {
197 - struct mip_priv *priv = domain->host_data;
198 - struct irq_fwspec fwspec;
199 + struct mip_priv *mip = domain->host_data;
200 + struct irq_fwspec fwspec = {0};
201 + unsigned int hwirq, i;
202 struct irq_data *irqd;
203 - int hwirq, ret, i;
204 -
205 - spin_lock(&priv->msi_map_lock);
206 + int irq, ret;
207
208 - hwirq = bitmap_find_free_region(priv->msi_map, priv->num_msis, ilog2(nr_irqs));
209 + irq = mip_alloc_hwirq(mip, nr_irqs);
210 + if (irq < 0)
211 + return irq;
212
213 - spin_unlock(&priv->msi_map_lock);
214 + hwirq = irq + mip->msi_offset;
215
216 - if (hwirq < 0)
217 - return -ENOSPC;
218 -
219 - hwirq += priv->msi_offset;
220 fwspec.fwnode = domain->parent->fwnode;
221 fwspec.param_count = 3;
222 fwspec.param[0] = 0;
223 - fwspec.param[1] = hwirq + priv->msi_base;
224 + fwspec.param[1] = hwirq + mip->msi_base;
225 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
226
227 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &fwspec);
228 if (ret)
229 - return ret;
230 + goto err_free_hwirq;
231
232 for (i = 0; i < nr_irqs; i++) {
233 irqd = irq_domain_get_irq_data(domain->parent, virq + i);
234 irqd->chip->irq_set_type(irqd, IRQ_TYPE_EDGE_RISING);
235
236 - irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
237 - &mip_irq_chip, priv);
238 + ret = irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
239 + &mip_middle_irq_chip, mip);
240 + if (ret)
241 + goto err_free;
242 +
243 irqd = irq_get_irq_data(virq + i);
244 irqd_set_single_target(irqd);
245 irqd_set_affinity_on_activate(irqd);
246 }
247
248 return 0;
249 -}
250 -
251 -static void mip_irq_domain_free(struct irq_domain *domain,
252 - unsigned int virq, unsigned int nr_irqs)
253 -{
254 - struct irq_data *d = irq_domain_get_irq_data(domain, virq);
255 - struct mip_priv *priv = irq_data_get_irq_chip_data(d);
256
257 +err_free:
258 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
259 - d->hwirq -= priv->msi_offset;
260 -
261 - spin_lock(&priv->msi_map_lock);
262 -
263 - bitmap_release_region(priv->msi_map, d->hwirq, ilog2(nr_irqs));
264 -
265 - spin_unlock(&priv->msi_map_lock);
266 +err_free_hwirq:
267 + mip_free_hwirq(mip, irq, nr_irqs);
268 + return ret;
269 }
270
271 -#if 0
272 -static int mip_irq_domain_activate(struct irq_domain *domain,
273 - struct irq_data *d, bool reserve)
274 +static void mip_middle_domain_free(struct irq_domain *domain, unsigned int virq,
275 + unsigned int nr_irqs)
276 {
277 - struct mip_priv *priv = irq_data_get_irq_chip_data(d);
278 - unsigned long flags;
279 - unsigned int irq = d->hwirq;
280 - void *__iomem reg = priv->base +
281 - ((irq < 32) ? MIP_INT_MASKL_HOST : MIP_INT_MASKH_HOST);
282 - u32 val;
283 -
284 - spin_lock_irqsave(&priv->hw_lock, flags);
285 - val = readl(reg);
286 - val &= ~(1 << (irq % 32)); // Clear the mask
287 - writel(val, reg);
288 - spin_unlock_irqrestore(&priv->hw_lock, flags);
289 - return 0;
290 -}
291 + struct irq_data *irqd = irq_domain_get_irq_data(domain, virq);
292 + struct mip_priv *mip;
293 + unsigned int hwirq;
294
295 -static void mip_irq_domain_deactivate(struct irq_domain *domain,
296 - struct irq_data *d)
297 -{
298 - struct mip_priv *priv = irq_data_get_irq_chip_data(d);
299 - unsigned long flags;
300 - unsigned int irq = d->hwirq - priv->msi_base;
301 - void *__iomem reg = priv->base +
302 - ((irq < 32) ? MIP_INT_MASKL_HOST : MIP_INT_MASKH_HOST);
303 - u32 val;
304 -
305 - spin_lock_irqsave(&priv->hw_lock, flags);
306 - val = readl(reg);
307 - val |= (1 << (irq % 32)); // Mask it out
308 - writel(val, reg);
309 - spin_unlock_irqrestore(&priv->hw_lock, flags);
310 + if (!irqd)
311 + return;
312 +
313 + mip = irq_data_get_irq_chip_data(irqd);
314 + hwirq = irqd_to_hwirq(irqd);
315 + irq_domain_free_irqs_parent(domain, virq, nr_irqs);
316 + mip_free_hwirq(mip, hwirq - mip->msi_offset, nr_irqs);
317 }
318 -#endif
319
320 -static const struct irq_domain_ops mip_irq_domain_ops = {
321 - .alloc = mip_irq_domain_alloc,
322 - .free = mip_irq_domain_free,
323 - //.activate = mip_irq_domain_activate,
324 - //.deactivate = mip_irq_domain_deactivate,
325 +static const struct irq_domain_ops mip_middle_domain_ops = {
326 + .select = msi_lib_irq_domain_select,
327 + .alloc = mip_middle_domain_alloc,
328 + .free = mip_middle_domain_free,
329 };
330
331 -static int mip_init_domains(struct mip_priv *priv,
332 - struct device_node *node)
333 -{
334 - struct irq_domain *middle_domain, *msi_domain, *gic_domain;
335 - struct device_node *gic_node;
336 -
337 - gic_node = of_irq_find_parent(node);
338 - if (!gic_node) {
339 - pr_err("Failed to find the GIC node\n");
340 - return -ENODEV;
341 - }
342 +#define MIP_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \
343 + MSI_FLAG_USE_DEF_CHIP_OPS | \
344 + MSI_FLAG_PCI_MSI_MASK_PARENT)
345 +
346 +#define MIP_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \
347 + MSI_FLAG_MULTI_PCI_MSI | \
348 + MSI_FLAG_PCI_MSIX)
349 +
350 +static const struct msi_parent_ops mip_msi_parent_ops = {
351 + .supported_flags = MIP_MSI_FLAGS_SUPPORTED,
352 + .required_flags = MIP_MSI_FLAGS_REQUIRED,
353 + .bus_select_token = DOMAIN_BUS_GENERIC_MSI,
354 + .bus_select_mask = MATCH_PCI_MSI,
355 + .prefix = "MIP-MSI-",
356 + .init_dev_msi_info = msi_lib_init_dev_msi_info,
357 +};
358
359 - gic_domain = irq_find_host(gic_node);
360 - if (!gic_domain) {
361 - pr_err("Failed to find the GIC domain\n");
362 - return -ENXIO;
363 - }
364 +static int mip_init_domains(struct mip_priv *mip, struct device_node *np)
365 +{
366 + struct irq_domain *middle;
367
368 - middle_domain = irq_domain_add_hierarchy(gic_domain, 0, 0, NULL,
369 - &mip_irq_domain_ops,
370 - priv);
371 - if (!middle_domain) {
372 - pr_err("Failed to create the MIP middle domain\n");
373 + middle = irq_domain_add_hierarchy(mip->parent, 0, mip->num_msis, np,
374 + &mip_middle_domain_ops, mip);
375 + if (!middle)
376 return -ENOMEM;
377 - }
378
379 - msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
380 - &mip_msi_domain_info,
381 - middle_domain);
382 - if (!msi_domain) {
383 - pr_err("Failed to create MSI domain\n");
384 - irq_domain_remove(middle_domain);
385 - return -ENOMEM;
386 - }
387 + irq_domain_update_bus_token(middle, DOMAIN_BUS_GENERIC_MSI);
388 + middle->dev = mip->dev;
389 + middle->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT;
390 + middle->msi_parent_ops = &mip_msi_parent_ops;
391 +
392 + /*
393 + * All MSI-X unmasked for the host, masked for the VPU, and edge-triggered.
394 + */
395 + writel(0, mip->base + MIP_INT_MASKL_HOST);
396 + writel(0, mip->base + MIP_INT_MASKH_HOST);
397 + writel(~0, mip->base + MIP_INT_MASKL_VPU);
398 + writel(~0, mip->base + MIP_INT_MASKH_VPU);
399 + writel(~0, mip->base + MIP_INT_CFGL_HOST);
400 + writel(~0, mip->base + MIP_INT_CFGH_HOST);
401
402 return 0;
403 }
404
405 -static int __init mip_of_msi_init(struct device_node *node,
406 - struct device_node *parent)
407 +static int mip_parse_dt(struct mip_priv *mip, struct device_node *np)
408 {
409 - struct mip_priv *priv;
410 - struct resource res;
411 + struct of_phandle_args args;
412 + u64 size;
413 int ret;
414
415 - priv = kzalloc(sizeof(*priv), GFP_KERNEL);
416 - if (!priv)
417 - return -ENOMEM;
418 + ret = of_property_read_u32(np, "brcm,msi-offset", &mip->msi_offset);
419 + if (ret)
420 + mip->msi_offset = 0;
421
422 - spin_lock_init(&priv->msi_map_lock);
423 - spin_lock_init(&priv->hw_lock);
424 + ret = of_parse_phandle_with_args(np, "msi-ranges", "#interrupt-cells",
425 + 0, &args);
426 + if (ret)
427 + return ret;
428
429 - ret = of_address_to_resource(node, 0, &res);
430 - if (ret) {
431 - pr_err("Failed to allocate resource\n");
432 - goto err_priv;
433 - }
434 + ret = of_property_read_u32_index(np, "msi-ranges", args.args_count + 1,
435 + &mip->num_msis);
436 + if (ret)
437 + goto err_put;
438
439 - if (of_property_read_u32(node, "brcm,msi-base-spi", &priv->msi_base)) {
440 - pr_err("Unable to parse MSI base\n");
441 - ret = -EINVAL;
442 - goto err_priv;
443 - }
444 + ret = of_property_read_reg(np, 1, &mip->msg_addr, &size);
445 + if (ret)
446 + goto err_put;
447 +
448 + mip->msi_base = args.args[1];
449
450 - if (of_property_read_u32(node, "brcm,msi-num-spis", &priv->num_msis)) {
451 - pr_err("Unable to parse MSI numbers\n");
452 + mip->parent = irq_find_host(args.np);
453 + if (!mip->parent)
454 ret = -EINVAL;
455 - goto err_priv;
456 - }
457
458 - if (of_property_read_u32(node, "brcm,msi-offset", &priv->msi_offset))
459 - priv->msi_offset = 0;
460 +err_put:
461 + of_node_put(args.np);
462 + return ret;
463 +}
464
465 - if (of_property_read_u64(node, "brcm,msi-pci-addr", &priv->msg_addr)) {
466 - pr_err("Unable to parse MSI address\n");
467 - ret = -EINVAL;
468 +static int __init mip_of_msi_init(struct device_node *node, struct device_node *parent)
469 +{
470 + struct platform_device *pdev;
471 + struct mip_priv *mip;
472 + int ret;
473 +
474 + pdev = of_find_device_by_node(node);
475 + of_node_put(node);
476 + if (!pdev)
477 + return -EPROBE_DEFER;
478 +
479 + mip = kzalloc(sizeof(*mip), GFP_KERNEL);
480 + if (!mip)
481 + return -ENOMEM;
482 +
483 + spin_lock_init(&mip->lock);
484 + mip->dev = &pdev->dev;
485 +
486 + ret = mip_parse_dt(mip, node);
487 + if (ret)
488 goto err_priv;
489 - }
490
491 - priv->base = ioremap(res.start, resource_size(&res));
492 - if (!priv->base) {
493 - pr_err("Failed to ioremap regs\n");
494 - ret = -ENOMEM;
495 + mip->base = of_iomap(node, 0);
496 + if (!mip->base) {
497 + ret = -ENXIO;
498 goto err_priv;
499 }
500
501 - priv->msi_map = kcalloc(BITS_TO_LONGS(priv->num_msis),
502 - sizeof(*priv->msi_map),
503 - GFP_KERNEL);
504 - if (!priv->msi_map) {
505 + mip->bitmap = bitmap_zalloc(mip->num_msis, GFP_KERNEL);
506 + if (!mip->bitmap) {
507 ret = -ENOMEM;
508 goto err_base;
509 }
510
511 - pr_debug("Registering %d msixs, starting at %d\n",
512 - priv->num_msis, priv->msi_base);
513 -
514 - /*
515 - * Begin with all MSI-Xs masked in for the host, masked out for the
516 - * VPU, and edge-triggered.
517 - */
518 - writel(0, priv->base + MIP_INT_MASKL_HOST);
519 - writel(0, priv->base + MIP_INT_MASKH_HOST);
520 - writel(~0, priv->base + MIP_INT_MASKL_VPU);
521 - writel(~0, priv->base + MIP_INT_MASKH_VPU);
522 - writel(~0, priv->base + MIP_INT_CFGL_HOST);
523 - writel(~0, priv->base + MIP_INT_CFGH_HOST);
524 -
525 - ret = mip_init_domains(priv, node);
526 - if (ret) {
527 - pr_err("Failed to allocate msi_map\n");
528 + ret = mip_init_domains(mip, node);
529 + if (ret)
530 goto err_map;
531 - }
532 +
533 + dev_dbg(&pdev->dev, "MIP: MSI-X count: %u, base: %u, offset: %u, msg_addr: %llx\n",
534 + mip->num_msis, mip->msi_base, mip->msi_offset, mip->msg_addr);
535
536 return 0;
537
538 err_map:
539 - kfree(priv->msi_map);
540 -
541 + bitmap_free(mip->bitmap);
542 err_base:
543 - iounmap(priv->base);
544 -
545 + iounmap(mip->base);
546 err_priv:
547 - kfree(priv);
548 -
549 - pr_err("%s: failed - err %d\n", __func__, ret);
550 -
551 + kfree(mip);
552 return ret;
553 }
554 -IRQCHIP_DECLARE(bcm_mip, "brcm,bcm2712-mip-intc", mip_of_msi_init);
555 +
556 +IRQCHIP_PLATFORM_DRIVER_BEGIN(mip_msi)
557 +IRQCHIP_MATCH("brcm,bcm2712-mip", mip_of_msi_init)
558 +IRQCHIP_PLATFORM_DRIVER_END(mip_msi)
559 +MODULE_DESCRIPTION("Broadcom BCM2712 MSI-X interrupt controller");
560 +MODULE_AUTHOR("Phil Elwell <phil@raspberrypi.com>");
561 +MODULE_AUTHOR("Stanimir Varbanov <svarbanov@suse.de>");
562 +MODULE_LICENSE("GPL");
Mirror of https://github.com/openwrt/openwrt.git