git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From 9d4ffbcfde283f2a87ea45128ddf7e6651facdd9 Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Fri, 7 Feb 2025 20:42:38 +0100
   4 Subject: [PATCH] mtd: rawnand: qcom: fix broken config in
   5  qcom_param_page_type_exec
   6
   7 Fix broken config in qcom_param_page_type_exec caused by copy-paste error
   8 from commit 0c08080fd71c ("mtd: rawnand: qcom: use FIELD_PREP and GENMASK")
   9
  10 In qcom_param_page_type_exec the value needs to be set to
  11 nandc->regs->cfg0 instead of host->cfg0. This wrong configuration caused
  12 the Qcom NANDC driver to malfunction on any device that makes use of it
  13 (IPQ806x, IPQ40xx, IPQ807x, IPQ60xx) with the following error:
  14
  15 [    0.885369] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xaa
  16 [    0.885909] nand: Micron NAND 256MiB 1,8V 8-bit
  17 [    0.892499] nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
  18 [    0.896823] nand: ECC (step, strength) = (512, 8) does not fit in OOB
  19 [    0.896836] qcom-nandc 79b0000.nand-controller: No valid ECC settings possible
  20 [    0.910996] bam-dma-engine 7984000.dma-controller: Cannot free busy channel
  21 [    0.918070] qcom-nandc: probe of 79b0000.nand-controller failed with error -28
  22
  23 Restore original configuration fix the problem and makes the driver work
  24 again.
  25
  26 Cc: stable@vger.kernel.org
  27 Fixes: 0c08080fd71c ("mtd: rawnand: qcom: use FIELD_PREP and GENMASK")
  28 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  29 ---
  30  drivers/mtd/nand/raw/qcom_nandc.c | 24 ++++++++++++------------
  31  1 file changed, 12 insertions(+), 12 deletions(-)
  32
  33 --- a/drivers/mtd/nand/raw/qcom_nandc.c
  34 +++ b/drivers/mtd/nand/raw/qcom_nandc.c
  35 @@ -1881,18 +1881,18 @@ static int qcom_param_page_type_exec(str
  36         nandc->regs->addr0 = 0;
  37         nandc->regs->addr1 = 0;
  38
  39 -       host->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, 0) |
  40 -                    FIELD_PREP(UD_SIZE_BYTES_MASK, 512) |
  41 -                    FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
  42 -                    FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
  43 +       nandc->regs->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, 0) |
  44 +                           FIELD_PREP(UD_SIZE_BYTES_MASK, 512) |
  45 +                           FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
  46 +                           FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
  47
  48 -       host->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
  49 -                    FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
  50 -                    FIELD_PREP(CS_ACTIVE_BSY, 0) |
  51 -                    FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
  52 -                    FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) |
  53 -                    FIELD_PREP(WIDE_FLASH, 0) |
  54 -                    FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
  55 +       nandc->regs->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
  56 +                           FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
  57 +                           FIELD_PREP(CS_ACTIVE_BSY, 0) |
  58 +                           FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
  59 +                           FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) |
  60 +                           FIELD_PREP(WIDE_FLASH, 0) |
  61 +                           FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
  62
  63         if (!nandc->props->qpic_version2)
  64                 nandc->regs->ecc_buf_cfg = cpu_to_le32(ECC_CFG_ECC_DISABLE);