git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From cf1ba3cb245020459f2ca446b7a7b199839f5d83 Mon Sep 17 00:00:00 2001
   2 From: Dan Carpenter <dan.carpenter@linaro.org>
   3 Date: Thu, 6 Mar 2025 12:40:01 +0300
   4 Subject: [PATCH] spi: spi-qpic-snand: Fix ECC_CFG_ECC_DISABLE shift in
   5  qcom_spi_read_last_cw()
   6
   7 The ECC_CFG_ECC_DISABLE define is BIT(0).  It's supposed to be used
   8 directly instead of used as a shifter.
   9
  10 Fixes: 7304d1909080 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface")
  11 Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
  12 Link: https://patch.msgid.link/2f4b0a0b-2c03-41c0-8a4a-3d789a83832d@stanley.mountain
  13 Signed-off-by: Mark Brown <broonie@kernel.org>
  14 ---
  15  drivers/spi/spi-qpic-snand.c | 2 +-
  16  1 file changed, 1 insertion(+), 1 deletion(-)
  17
  18 --- a/drivers/spi/spi-qpic-snand.c
  19 +++ b/drivers/spi/spi-qpic-snand.c
  20 @@ -514,7 +514,7 @@ static int qcom_spi_read_last_cw(struct
  21         cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
  22                 0 << CW_PER_PAGE;
  23         cfg1 = ecc_cfg->cfg1_raw;
  24 -       ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
  25 +       ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
  26
  27         snandc->regs->cmd = snandc->qspi->cmd;
  28         snandc->regs->cfg0 = cpu_to_le32(cfg0);