git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From a7e8397e2db6133e3435054a3f312dbd9cab05ed Mon Sep 17 00:00:00 2001
   2 From: Luo Jie <quic_luoj@quicinc.com>
   3 Date: Tue, 20 Aug 2024 22:02:43 +0800
   4 Subject: [PATCH] clk: qcom: Add CMN PLL clock controller driver for IPQ
   5  SoC
   6
   7 The CMN PLL clock controller supplies clocks to the hardware
   8 blocks that together make up the Ethernet function on Qualcomm
   9 IPQ SoCs. The driver is initially supported for IPQ9574 SoC.
  10
  11 The CMN PLL clock controller expects a reference input clock
  12 from the on-board Wi-Fi block acting as clock source. The input
  13 reference clock needs to be configured to one of the supported
  14 clock rates.
  15
  16 The controller supplies a number of fixed-rate output clocks.
  17 For the IPQ9574, there is one output clock of 353 MHZ to PPE
  18 (Packet Process Engine) hardware block, three 50 MHZ output
  19 clocks and an additional 25 MHZ output clock supplied to the
  20 connected Ethernet devices.
  21
  22 Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
  23 ---
  24  drivers/clk/qcom/Kconfig           |  10 ++
  25  drivers/clk/qcom/Makefile          |   1 +
  26  drivers/clk/qcom/clk-ipq-cmn-pll.c | 227 +++++++++++++++++++++++++++++
  27  3 files changed, 238 insertions(+)
  28  create mode 100644 drivers/clk/qcom/clk-ipq-cmn-pll.c
  29
  30 --- a/drivers/clk/qcom/Kconfig
  31 +++ b/drivers/clk/qcom/Kconfig
  32 @@ -139,6 +139,16 @@ config IPQ_APSS_6018
  33           Say Y if you want to support CPU frequency scaling on
  34           ipq based devices.
  35
  36 +config IPQ_CMN_PLL
  37 +       tristate "IPQ CMN PLL Clock Controller"
  38 +       depends on IPQ_GCC_9574
  39 +       help
  40 +         Support for CMN PLL clock controller on IPQ platform. The
  41 +         CMN PLL feeds the reference clocks to the Ethernet devices
  42 +         based on IPQ SoC.
  43 +         Say Y or M if you want to support CMN PLL clock on the IPQ
  44 +         based devices.
  45 +
  46  config IPQ_GCC_4019
  47         tristate "IPQ4019 Global Clock Controller"
  48         help
  49 --- a/drivers/clk/qcom/Makefile
  50 +++ b/drivers/clk/qcom/Makefile
  51 @@ -23,6 +23,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8
  52  obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
  53  obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
  54  obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
  55 +obj-$(CONFIG_IPQ_CMN_PLL) += clk-ipq-cmn-pll.o
  56  obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
  57  obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o
  58  obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o
  59 --- /dev/null
  60 +++ b/drivers/clk/qcom/clk-ipq-cmn-pll.c
  61 @@ -0,0 +1,227 @@
  62 +// SPDX-License-Identifier: GPL-2.0-only
  63 +/*
  64 + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  65 + */
  66 +
  67 +/*
  68 + * CMN PLL block expects the reference clock from on-board Wi-Fi block, and
  69 + * supplies fixed rate clocks as output to the Ethernet hardware blocks.
  70 + * The Ethernet related blocks include PPE (packet process engine) and the
  71 + * external connected PHY (or switch) chip receiving clocks from the CMN PLL.
  72 + *
  73 + * On the IPQ9574 SoC, There are three clocks with 50 MHZ, one clock with
  74 + * 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch),
  75 + * and one clock with 353 MHZ to PPE.
  76 + *
  77 + *               +---------+
  78 + *               |   GCC   |
  79 + *               +--+---+--+
  80 + *           AHB CLK|   |SYS CLK
  81 + *                  V   V
  82 + *          +-------+---+------+
  83 + *          |                  +-------------> eth0-50mhz
  84 + * REF CLK  |     IPQ9574      |
  85 + * -------->+                  +-------------> eth1-50mhz
  86 + *          |  CMN PLL block   |
  87 + *          |                  +-------------> eth2-50mhz
  88 + *          |                  |
  89 + *          +---------+--------+-------------> eth-25mhz
  90 + *                    |
  91 + *                    V
  92 + *                    ppe-353mhz
  93 + */
  94 +
  95 +#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
  96 +#include <linux/bitfield.h>
  97 +#include <linux/clk.h>
  98 +#include <linux/clk-provider.h>
  99 +#include <linux/delay.h>
 100 +#include <linux/io.h>
 101 +#include <linux/of.h>
 102 +#include <linux/of_address.h>
 103 +#include <linux/platform_device.h>
 104 +#include <linux/slab.h>
 105 +
 106 +#define CMN_PLL_REFCLK_SRC_SELECTION           0x28
 107 +#define CMN_PLL_REFCLK_SRC_DIV                 GENMASK(9, 8)
 108 +
 109 +#define CMN_PLL_REFCLK_CONFIG                  0x784
 110 +#define CMN_PLL_REFCLK_EXTERNAL                        BIT(9)
 111 +#define CMN_PLL_REFCLK_DIV                     GENMASK(8, 4)
 112 +#define CMN_PLL_REFCLK_INDEX                   GENMASK(3, 0)
 113 +
 114 +#define CMN_PLL_POWER_ON_AND_RESET             0x780
 115 +#define CMN_ANA_EN_SW_RSTN                     BIT(6)
 116 +
 117 +/**
 118 + * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information
 119 + * @id:        Clock specifier to be supplied
 120 + * @name: Clock name to be registered
 121 + * @rate: Clock rate
 122 + */
 123 +struct cmn_pll_fixed_output_clk {
 124 +       unsigned int            id;
 125 +       const char              *name;
 126 +       const unsigned long     rate;
 127 +};
 128 +
 129 +#define CLK_PLL_OUTPUT(_id, _name, _rate) {            \
 130 +       .id = _id,                                      \
 131 +       .name = _name,                                  \
 132 +       .rate = _rate,                                  \
 133 +}
 134 +
 135 +static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = {
 136 +       CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL),
 137 +       CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL),
 138 +       CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),
 139 +       CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),
 140 +       CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
 141 +};
 142 +
 143 +static int ipq_cmn_pll_config(struct device *dev, unsigned long parent_rate)
 144 +{
 145 +       void __iomem *base;
 146 +       u32 val;
 147 +
 148 +       base = devm_of_iomap(dev, dev->of_node, 0, NULL);
 149 +       if (IS_ERR(base))
 150 +               return PTR_ERR(base);
 151 +
 152 +       val = readl(base + CMN_PLL_REFCLK_CONFIG);
 153 +       val &= ~(CMN_PLL_REFCLK_EXTERNAL | CMN_PLL_REFCLK_INDEX);
 154 +
 155 +       /*
 156 +        * Configure the reference input clock selection as per the given rate.
 157 +        * The output clock rates are always of fixed value.
 158 +        */
 159 +       switch (parent_rate) {
 160 +       case 25000000:
 161 +               val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 3);
 162 +               break;
 163 +       case 31250000:
 164 +               val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 4);
 165 +               break;
 166 +       case 40000000:
 167 +               val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 6);
 168 +               break;
 169 +       case 48000000:
 170 +               val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7);
 171 +               break;
 172 +       case 50000000:
 173 +               val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 8);
 174 +               break;
 175 +       case 96000000:
 176 +               val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7);
 177 +               val &= ~CMN_PLL_REFCLK_DIV;
 178 +               val |= FIELD_PREP(CMN_PLL_REFCLK_DIV, 2);
 179 +               break;
 180 +       default:
 181 +               return -EINVAL;
 182 +       }
 183 +
 184 +       writel(val, base + CMN_PLL_REFCLK_CONFIG);
 185 +
 186 +       /* Update the source clock rate selection. Only 96 MHZ uses 0. */
 187 +       val = readl(base + CMN_PLL_REFCLK_SRC_SELECTION);
 188 +       val &= ~CMN_PLL_REFCLK_SRC_DIV;
 189 +       if (parent_rate != 96000000)
 190 +               val |= FIELD_PREP(CMN_PLL_REFCLK_SRC_DIV, 1);
 191 +
 192 +       writel(val, base + CMN_PLL_REFCLK_SRC_SELECTION);
 193 +
 194 +       /*
 195 +        * Reset the CMN PLL block by asserting/de-asserting for 100 ms
 196 +        * each, to ensure the updated configurations take effect.
 197 +        */
 198 +       val = readl(base + CMN_PLL_POWER_ON_AND_RESET);
 199 +       val &= ~CMN_ANA_EN_SW_RSTN;
 200 +       writel(val, base);
 201 +       msleep(100);
 202 +
 203 +       val |= CMN_ANA_EN_SW_RSTN;
 204 +       writel(val, base + CMN_PLL_POWER_ON_AND_RESET);
 205 +       msleep(100);
 206 +
 207 +       return 0;
 208 +}
 209 +
 210 +static int ipq_cmn_pll_clk_register(struct device *dev, const char *parent)
 211 +{
 212 +       const struct cmn_pll_fixed_output_clk *fixed_clk;
 213 +       struct clk_hw_onecell_data *data;
 214 +       unsigned int num_clks;
 215 +       struct clk_hw *hw;
 216 +       int i;
 217 +
 218 +       num_clks = ARRAY_SIZE(ipq9574_output_clks);
 219 +       fixed_clk = ipq9574_output_clks;
 220 +
 221 +       data = devm_kzalloc(dev, struct_size(data, hws, num_clks), GFP_KERNEL);
 222 +       if (!data)
 223 +               return -ENOMEM;
 224 +
 225 +       for (i = 0; i < num_clks; i++) {
 226 +               hw = devm_clk_hw_register_fixed_rate(dev, fixed_clk[i].name,
 227 +                                                    parent, 0,
 228 +                                                    fixed_clk[i].rate);
 229 +               if (IS_ERR(hw))
 230 +                       return PTR_ERR(hw);
 231 +
 232 +               data->hws[fixed_clk[i].id] = hw;
 233 +       }
 234 +       data->num = num_clks;
 235 +
 236 +       return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data);
 237 +}
 238 +
 239 +static int ipq_cmn_pll_clk_probe(struct platform_device *pdev)
 240 +{
 241 +       struct device *dev = &pdev->dev;
 242 +       struct clk *clk;
 243 +       int ret;
 244 +
 245 +       /*
 246 +        * To access the CMN PLL registers, the GCC AHB & SYSY clocks
 247 +        * for CMN PLL block need to be enabled.
 248 +        */
 249 +       clk = devm_clk_get_enabled(dev, "ahb");
 250 +       if (IS_ERR(clk))
 251 +               return dev_err_probe(dev, PTR_ERR(clk),
 252 +                                    "Enable AHB clock failed\n");
 253 +
 254 +       clk = devm_clk_get_enabled(dev, "sys");
 255 +       if (IS_ERR(clk))
 256 +               return dev_err_probe(dev, PTR_ERR(clk),
 257 +                                    "Enable SYS clock failed\n");
 258 +
 259 +       clk = devm_clk_get(dev, "ref");
 260 +       if (IS_ERR(clk))
 261 +               return dev_err_probe(dev, PTR_ERR(clk),
 262 +                                    "Get reference clock failed\n");
 263 +
 264 +       /* Configure CMN PLL to apply the reference clock. */
 265 +       ret = ipq_cmn_pll_config(dev, clk_get_rate(clk));
 266 +       if (ret)
 267 +               return dev_err_probe(dev, ret, "Configure CMN PLL failed\n");
 268 +
 269 +       return ipq_cmn_pll_clk_register(dev, __clk_get_name(clk));
 270 +}
 271 +
 272 +static const struct of_device_id ipq_cmn_pll_clk_ids[] = {
 273 +       { .compatible = "qcom,ipq9574-cmn-pll", },
 274 +       { }
 275 +};
 276 +
 277 +static struct platform_driver ipq_cmn_pll_clk_driver = {
 278 +       .probe = ipq_cmn_pll_clk_probe,
 279 +       .driver = {
 280 +               .name = "ipq_cmn_pll",
 281 +               .of_match_table = ipq_cmn_pll_clk_ids,
 282 +       },
 283 +};
 284 +
 285 +module_platform_driver(ipq_cmn_pll_clk_driver);
 286 +
 287 +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPQ CMN PLL Driver");
 288 +MODULE_LICENSE("GPL");