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1 From 65fddc7301f52470fd846acede96d240a1902e67 Mon Sep 17 00:00:00 2001
2 From: Jonathan Bell <jonathan@raspberrypi.com>
3 Date: Fri, 5 Jul 2024 14:00:38 +0100
4 Subject: [PATCH 1146/1215] drivers: dwc_otg: use C11 style variable array
5 declarations
6
7 The kernel C standard changed in 5.18.
8
9 Remove a layer of indirection around the FIQ bounce buffers, be consistent
10 with pointers to FIQ bounce buffers, and remove open-coded 32-bit clamping
11 of DMA addresses.
12
13 Also remove a pointless fiq_state initialisation loop.
14
15 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
16 ---
17 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 12 ++++----
18 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h | 8 ++---
19 drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 34 ++++++++++-----------
20 drivers/usb/host/dwc_otg/dwc_otg_hcd.h | 4 +--
21 drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 4 +--
22 5 files changed, 28 insertions(+), 34 deletions(-)
23
24 --- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
25 +++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
26 @@ -240,8 +240,8 @@ static int notrace fiq_increment_dma_buf
27 hcdma_data_t hcdma;
28 int i = st->channel[n].dma_info.index;
29 int len;
30 - struct fiq_dma_blob *blob =
31 - (struct fiq_dma_blob *)(uintptr_t)st->dma_base;
32 + struct fiq_dma_channel *split_dma =
33 + (struct fiq_dma_channel *)(uintptr_t)st->dma_base;
34
35 len = fiq_get_xfer_len(st, n);
36 fiq_print(FIQDBG_INT, st, "LEN: %03d", len);
37 @@ -250,7 +250,7 @@ static int notrace fiq_increment_dma_buf
38 if (i > 6)
39 BUG();
40
41 - hcdma.d32 = (u32)(uintptr_t)&blob->channel[n].index[i].buf[0];
42 + hcdma.d32 = lower_32_bits((uintptr_t)&split_dma[n].index[i].buf[0]);
43 FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);
44 st->channel[n].dma_info.index = i;
45 return 0;
46 @@ -290,8 +290,8 @@ static int notrace fiq_iso_out_advance(s
47 hcsplt_data_t hcsplt;
48 hctsiz_data_t hctsiz;
49 hcdma_data_t hcdma;
50 - struct fiq_dma_blob *blob =
51 - (struct fiq_dma_blob *)(uintptr_t)st->dma_base;
52 + struct fiq_dma_channel *split_dma =
53 + (struct fiq_dma_channel *)(uintptr_t)st->dma_base;
54 int last = 0;
55 int i = st->channel[n].dma_info.index;
56
57 @@ -303,7 +303,7 @@ static int notrace fiq_iso_out_advance(s
58 last = 1;
59
60 /* New DMA address - address of bounce buffer referred to in index */
61 - hcdma.d32 = (u32)(uintptr_t)blob->channel[n].index[i].buf;
62 + hcdma.d32 = lower_32_bits((uintptr_t)&split_dma[n].index[i].buf[0]);
63 //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA);
64 //hcdma.d32 += st->channel[n].dma_info.slot_len[i];
65 fiq_print(FIQDBG_INT, st, "LAST: %01d ", last);
66 --- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
67 +++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
68 @@ -263,10 +263,6 @@ struct fiq_dma_channel {
69 struct fiq_split_dma_slot index[6];
70 } __attribute__((packed));
71
72 -struct fiq_dma_blob {
73 - struct fiq_dma_channel channel[0];
74 -} __attribute__((packed));
75 -
76 /**
77 * struct fiq_hs_isoc_info - USB2.0 isochronous data
78 * @iso_frame: Pointer to the array of OTG URB iso_frame_descs.
79 @@ -352,7 +348,7 @@ struct fiq_state {
80 mphi_regs_t mphi_regs;
81 void *dwc_regs_base;
82 dma_addr_t dma_base;
83 - struct fiq_dma_blob *fiq_dmab;
84 + struct fiq_dma_channel *fiq_dmab;
85 void *dummy_send;
86 dma_addr_t dummy_send_dma;
87 gintmsk_data_t gintmsk_saved;
88 @@ -365,7 +361,7 @@ struct fiq_state {
89 char * buffer;
90 unsigned int bufsiz;
91 #endif
92 - struct fiq_channel_state channel[0];
93 + struct fiq_channel_state channel[];
94 };
95
96 #ifdef CONFIG_ARM64
97 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
98 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
99 @@ -58,6 +58,7 @@ static int last_sel_trans_num_avail_hc_a
100 static int last_sel_trans_num_avail_hc_at_end = 0;
101 #endif /* DEBUG_HOST_CHANNELS */
102
103 +static_assert(FIQ_PASSTHROUGH == 0);
104
105 dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
106 {
107 @@ -876,7 +877,7 @@ void dwc_otg_hcd_power_up(void *ptr)
108 void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num)
109 {
110 struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
111 - struct fiq_dma_blob *blob = hcd->fiq_dmab;
112 + struct fiq_dma_channel *split_dma = hcd->fiq_dmab;
113 int i;
114
115 st->fsm = FIQ_PASSTHROUGH;
116 @@ -898,7 +899,7 @@ void dwc_otg_cleanup_fiq_channel(dwc_otg
117 st->hs_isoc_info.iso_desc = NULL;
118 st->hs_isoc_info.nrframes = 0;
119
120 - DWC_MEMSET(&blob->channel[num].index[0], 0x6b, 1128);
121 + DWC_MEMSET(&split_dma[num].index[0], 0x6b, 1128);
122 }
123
124 /**
125 @@ -1045,9 +1046,6 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd
126 spin_lock_init(&hcd->fiq_state->lock);
127 #endif
128
129 - for (i = 0; i < num_channels; i++) {
130 - hcd->fiq_state->channel[i].fsm = FIQ_PASSTHROUGH;
131 - }
132 hcd->fiq_state->dummy_send = DWC_DMA_ALLOC_ATOMIC(dev, 16,
133 &hcd->fiq_state->dummy_send_dma);
134
135 @@ -1561,7 +1559,7 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_h
136 int frame_length, i = 0;
137 uint8_t *ptr = NULL;
138 dwc_hc_t *hc = qh->channel;
139 - struct fiq_dma_blob *blob;
140 + struct fiq_dma_channel *split_dma;
141 struct dwc_otg_hcd_iso_packet_desc *frame_desc;
142
143 for (i = 0; i < 6; i++) {
144 @@ -1576,10 +1574,10 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_h
145 * Pointer arithmetic on hcd->fiq_state->dma_base (a dma_addr_t)
146 * to point it to the correct offset in the allocated buffers.
147 */
148 - blob = (struct fiq_dma_blob *)
149 + split_dma = (struct fiq_dma_channel *)
150 (uintptr_t)hcd->fiq_state->dma_base;
151 - st->hcdma_copy.d32 =(u32)(uintptr_t)
152 - blob->channel[hc->hc_num].index[0].buf;
153 + st->hcdma_copy.d32 = lower_32_bits((uintptr_t)
154 + &split_dma[hc->hc_num].index[0].buf[0]);
155
156 /* Calculate the max number of CSPLITS such that the FIQ can time out
157 * a transaction if it fails.
158 @@ -1600,7 +1598,7 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_h
159 frame_length = frame_desc->length;
160
161 /* Virtual address for bounce buffers */
162 - blob = hcd->fiq_dmab;
163 + split_dma = hcd->fiq_dmab;
164
165 ptr = qtd->urb->buf + frame_desc->offset;
166 if (frame_length == 0) {
167 @@ -1613,11 +1611,11 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_h
168 } else {
169 do {
170 if (frame_length <= 188) {
171 - dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, frame_length);
172 + dwc_memcpy(&split_dma[hc->hc_num].index[i].buf[0], ptr, frame_length);
173 st->dma_info.slot_len[i] = frame_length;
174 ptr += frame_length;
175 } else {
176 - dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, 188);
177 + dwc_memcpy(&split_dma[hc->hc_num].index[i].buf[0], ptr, 188);
178 st->dma_info.slot_len[i] = 188;
179 ptr += 188;
180 }
181 @@ -1634,10 +1632,10 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_h
182 * dma_addr_t) to point it to the correct offset in the
183 * allocated buffers.
184 */
185 - blob = (struct fiq_dma_blob *)
186 + split_dma = (struct fiq_dma_channel *)
187 (uintptr_t)hcd->fiq_state->dma_base;
188 - st->hcdma_copy.d32 = (u32)(uintptr_t)
189 - blob->channel[hc->hc_num].index[0].buf;
190 + st->hcdma_copy.d32 = lower_32_bits((uintptr_t)
191 + &split_dma[hc->hc_num].index[0].buf[0]);
192
193 /* fixup xfersize to the actual packet size */
194 st->hctsiz_copy.b.pid = 0;
195 @@ -1917,14 +1915,14 @@ int fiq_fsm_queue_split_transaction(dwc_
196 if (hc->align_buff) {
197 st->hcdma_copy.d32 = hc->align_buff;
198 } else {
199 - st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
200 + st->hcdma_copy.d32 = lower_32_bits((uintptr_t)hc->xfer_buff);
201 }
202 }
203 } else {
204 if (hc->align_buff) {
205 st->hcdma_copy.d32 = hc->align_buff;
206 } else {
207 - st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
208 + st->hcdma_copy.d32 = lower_32_bits((uintptr_t)hc->xfer_buff);
209 }
210 }
211 /* The FIQ depends upon no other interrupts being enabled except channel halt.
212 @@ -1944,7 +1942,7 @@ int fiq_fsm_queue_split_transaction(dwc_
213 if (hc->align_buff) {
214 st->hcdma_copy.d32 = hc->align_buff;
215 } else {
216 - st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
217 + st->hcdma_copy.d32 = lower_32_bits((uintptr_t)hc->xfer_buff);
218 }
219 }
220 DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32);
221 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.h
222 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.h
223 @@ -88,7 +88,7 @@ struct dwc_otg_hcd_urb {
224 uint32_t flags;
225 uint16_t interval;
226 struct dwc_otg_hcd_pipe_info pipe_info;
227 - struct dwc_otg_hcd_iso_packet_desc iso_descs[0];
228 + struct dwc_otg_hcd_iso_packet_desc iso_descs[];
229 };
230
231 static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe)
232 @@ -592,7 +592,7 @@ struct dwc_otg_hcd {
233 struct fiq_state *fiq_state;
234
235 /** Virtual address for split transaction DMA bounce buffers */
236 - struct fiq_dma_blob *fiq_dmab;
237 + struct fiq_dma_channel *fiq_dmab;
238
239 #ifdef DEBUG
240 uint32_t frrem_samples;
241 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
242 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
243 @@ -2332,7 +2332,7 @@ void dwc_otg_fiq_unmangle_isoc(dwc_otg_h
244 int dwc_otg_fiq_unsetup_per_dma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num)
245 {
246 dwc_hc_t *hc = qh->channel;
247 - struct fiq_dma_blob *blob = hcd->fiq_dmab;
248 + struct fiq_dma_channel *split_dma = hcd->fiq_dmab;
249 struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
250 uint8_t *ptr = NULL;
251 int index = 0, len = 0;
252 @@ -2352,7 +2352,7 @@ int dwc_otg_fiq_unsetup_per_dma(dwc_otg_
253
254 for (i = 0; i < st->dma_info.index; i++) {
255 len += st->dma_info.slot_len[i];
256 - dwc_memcpy(ptr, &blob->channel[num].index[i].buf[0], st->dma_info.slot_len[i]);
257 + dwc_memcpy(ptr, &split_dma[num].index[i].buf[0], st->dma_info.slot_len[i]);
258 ptr += st->dma_info.slot_len[i];
259 }
260 return len;
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