git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From 0d4d8e6f47ef22ea6b3041b4c0cb27b4ed4bf188 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Tue, 17 Dec 2024 16:39:23 +0800
   4 Subject: [PATCH 03/10] net: mediatek: use correct register field for SGMII
   5  speed selection
   6
   7 The register field for SGMII speed selection is a 2-bit field with
   8 value 0 for 1Gbps and 1 for 2.5Gbps (2/3 are reserved).
   9 So it's necessary to set both bits instead of just setting/clearing
  10 only the lower bit.
  11
  12 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  13 ---
  14  drivers/net/mtk_eth.c | 12 ++++++------
  15  drivers/net/mtk_eth.h |  3 ++-
  16  2 files changed, 8 insertions(+), 7 deletions(-)
  17
  18 --- a/drivers/net/mtk_eth.c
  19 +++ b/drivers/net/mtk_eth.c
  20 @@ -835,8 +835,8 @@ static int mt7531_port_sgmii_init(struct
  21         }
  22
  23         /* Set SGMII GEN2 speed(2.5G) */
  24 -       mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
  25 -                      SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
  26 +       mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK,
  27 +                      FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500));
  28
  29         /* Disable SGMII AN */
  30         mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port),
  31 @@ -1281,8 +1281,7 @@ static int mtk_phy_probe(struct udevice
  32  static void mtk_sgmii_an_init(struct mtk_eth_priv *priv)
  33  {
  34         /* Set SGMII GEN1 speed(1G) */
  35 -       clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
  36 -                       SGMSYS_SPEED_2500, 0);
  37 +       clrbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, SGMSYS_SPEED_MASK);
  38
  39         /* Enable SGMII AN */
  40         setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
  41 @@ -1305,8 +1304,9 @@ static void mtk_sgmii_an_init(struct mtk
  42  static void mtk_sgmii_force_init(struct mtk_eth_priv *priv)
  43  {
  44         /* Set SGMII GEN2 speed(2.5G) */
  45 -       setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
  46 -                    SGMSYS_SPEED_2500);
  47 +       clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
  48 +                       SGMSYS_SPEED_MASK,
  49 +                       FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500));
  50
  51         /* Disable SGMII AN */
  52         clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
  53 --- a/drivers/net/mtk_eth.h
  54 +++ b/drivers/net/mtk_eth.h
  55 @@ -108,7 +108,8 @@ enum mkt_eth_capabilities {
  56
  57  #define SGMSYS_GEN2_SPEED              0x2028
  58  #define SGMSYS_GEN2_SPEED_V2           0x128
  59 -#define SGMSYS_SPEED_2500              BIT(2)
  60 +#define SGMSYS_SPEED_MASK              GENMASK(3, 2)
  61 +#define SGMSYS_SPEED_2500              1
  62
  63  /* USXGMII subsystem config registers */
  64  /* Register to control USXGMII XFI PLL digital */