git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From 2b5de12af9bb390239d5f3385c49e0c34f335de8 Mon Sep 17 00:00:00 2001
   2 From: Jonathan Bell <jonathan@raspberrypi.com>
   3 Date: Fri, 27 Sep 2024 10:59:02 +0100
   4 Subject: [PATCH 1289/1350] dts: align PCI BAR allocation on bcm2711 and
   5  bcm2712 to start at 2GB
   6
   7 Fold the Pi 5 mmio-hi compatibility option into the base DTB, and
   8 shuffle the single MMIO window on bcm2711 to match.
   9
  10 Certain devices cannot handle low addresses, e.g. by failing to
  11 enumerate or failing to route the traffic appropriately.
  12
  13 Link: https://github.com/raspberrypi/linux/issues/6134
  14 Link: https://github.com/raspberrypi/linux/issues/6278
  15
  16 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  17 ---
  18  .../arm/boot/dts/broadcom/bcm2711-rpi-ds.dtsi |  6 +++---
  19  arch/arm/boot/dts/overlays/README             |  2 --
  20  .../overlays/pciex1-compat-pi5-overlay.dts    | 20 -------------------
  21  arch/arm64/boot/dts/broadcom/bcm2712.dtsi     | 10 ++++++----
  22  4 files changed, 9 insertions(+), 29 deletions(-)
  23
  24 --- a/arch/arm/boot/dts/broadcom/bcm2711-rpi-ds.dtsi
  25 +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-ds.dtsi
  26 @@ -123,7 +123,7 @@
  27
  28         ranges = <0x0 0x7c000000  0x0 0xfc000000  0x0 0x03800000>,
  29                  <0x0 0x40000000  0x0 0xff800000  0x0 0x00800000>,
  30 -                <0x6 0x00000000  0x6 0x00000000  0x0 0x40000000>,
  31 +                <0x6 0x00000000  0x6 0x00000000  0x0 0x80000000>,
  32                  <0x0 0x00000000  0x0 0x00000000  0x0 0xfc000000>;
  33         dma-ranges = <0x4 0x7c000000  0x0 0xfc000000  0x0 0x03800000>,
  34                      <0x0 0x00000000  0x0 0x00000000  0x4 0x00000000>;
  35 @@ -167,8 +167,8 @@
  36
  37  &pcie0 {
  38         reg = <0x0 0x7d500000  0x0 0x9310>;
  39 -       ranges = <0x02000000 0x0 0xc0000000 0x6 0x00000000
  40 -                 0x0 0x40000000>;
  41 +       ranges = <0x02000000 0x0 0x80000000 0x6 0x00000000
  42 +                 0x0 0x80000000>;
  43  };
  44
  45  &genet {
  46 --- a/arch/arm/boot/dts/overlays/README
  47 +++ b/arch/arm/boot/dts/overlays/README
  48 @@ -3617,8 +3617,6 @@ Params: l1ss                    Enable A
  49                                  the MSI-MIP peripheral. Use if a) more than 8
  50                                  interrupt vectors are required or b) the EP
  51                                  requires DMA and MSI addresses to be 32bit.
  52 -        mmio-hi                 Move the start of outbound 32bit addresses to
  53 -                                2GB and expand 64bit outbound space to 14GB.
  54
  55
  56  [ The pcf2127-rtc overlay has been deleted. See i2c-rtc. ]
  57 --- a/arch/arm/boot/dts/overlays/pciex1-compat-pi5-overlay.dts
  58 +++ b/arch/arm/boot/dts/overlays/pciex1-compat-pi5-overlay.dts
  59 @@ -32,29 +32,9 @@
  60                 };
  61         };
  62
  63 -       /*
  64 -        * Shift the start of the 32bit outbound window to 2GB,
  65 -        * so there are no BARs starting at 0x0. Expand the 64bit
  66 -        * outbound window to use the spare 2GB.
  67 -        */
  68 -       fragment@3 {
  69 -               target = <&pciex1>;
  70 -               __dormant__ {
  71 -                       #address-cells = <3>;
  72 -                       #size-cells = <2>;
  73 -                       ranges = <0x02000000 0x00 0x80000000
  74 -                                 0x1b 0x80000000
  75 -                                 0x00 0x7ffffffc>,
  76 -                                <0x43000000 0x04 0x00000000
  77 -                                 0x18 0x00000000
  78 -                                 0x03 0x80000000>;
  79 -               };
  80 -       };
  81 -
  82         __overrides__ {
  83                 l1ss = <0>, "+0";
  84                 no-l0s = <0>, "+1";
  85                 no-mip = <0>, "+2";
  86 -               mmio-hi = <0>, "+3";
  87         };
  88  };
  89 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
  90 +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
  91 @@ -1052,12 +1052,14 @@
  92                         msi-controller;
  93                         msi-parent = <&mip1>;
  94
  95 -                       ranges = <0x02000000 0x00 0x00000000
  96 -                                 0x1b 0x00000000
  97 -                                 0x00 0xfffffffc>,
  98 +                       // 2GB, 32-bit, non-prefetchable at PCIe 00_80000000
  99 +                       ranges = <0x02000000 0x00 0x80000000
 100 +                                 0x1b 0x80000000
 101 +                                 0x00 0x80000000>,
 102 +                       // 14GB, 64-bit, prefetchable at PCIe 04_00000000
 103                                  <0x43000000 0x04 0x00000000
 104                                   0x18 0x00000000
 105 -                                 0x03 0x00000000>;
 106 +                                 0x03 0x80000000>;
 107
 108                         dma-ranges = <0x03000000 0x10 0x00000000
 109                                       0x00 0x00000000