git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From ba365c3d23411620d86b5baf621c8f5a4000ab33 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Tue, 17 Dec 2024 16:39:20 +0800
   4 Subject: [PATCH 02/10] arm: dts: mt7629: fix sgmii clock selection for
   5  ethernet
   6
   7 Setup correct parent of clock CLK_TOP_SGMII_REF_1_SEL to allow
   8 sgmiisys1 work correctly.
   9
  10 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  11 ---
  12  arch/arm/dts/mt7629.dtsi | 4 +++-
  13  1 file changed, 3 insertions(+), 1 deletion(-)
  14
  15 --- a/arch/arm/dts/mt7629.dtsi
  16 +++ b/arch/arm/dts/mt7629.dtsi
  17 @@ -314,8 +314,10 @@
  18                                 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
  19                                 "sgmii_ck", "eth2pll";
  20                 assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
  21 -                                 <&topckgen CLK_TOP_F10M_REF_SEL>;
  22 +                                 <&topckgen CLK_TOP_F10M_REF_SEL>,
  23 +                                 <&topckgen CLK_TOP_SGMII_REF_1_SEL>;
  24                 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
  25 +                                        <&topckgen CLK_TOP_SYSPLL4_D16>,
  26                                          <&topckgen CLK_TOP_SGMIIPLL_D2>;
  27                 power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
  28                 resets = <&ethsys ETHSYS_FE_RST>;