git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From 85cc26d5496f073fc7e5dc33f8c9fd5c7aea93c6 Mon Sep 17 00:00:00 2001
   2 From: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
   3 Date: Mon, 22 Apr 2024 13:06:21 +0100
   4 Subject: [PATCH 1050/1085] DRM: rp1: rp1-dsi: Fix escape clock divider and
   5  timeouts.
   6
   7 Escape clock divider was fixed at 5, which is correct at 800Mbps/lane
   8 but increasingly out of spec for higher rates. Compute it correctly.
   9
  10 High speed timeout was fixed at 5*512 == 2560 byte-clocks per lane.
  11 Compute it conservatively to be 8/7 times the line period (assuming
  12 there will be a transition to LP some time during each scanline?)
  13 keeping the old value as a lower bound. Increase LPRX TO to 1024,
  14 and BTA TO to 0xb00 (same value as in bridge/synopsys/dw-mipi-dsi).
  15
  16 (No change to LP_CMD_TIM. To do: compute this correctly.)
  17
  18 Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
  19 ---
  20  drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c | 39 ++++++++++++++---------
  21  1 file changed, 24 insertions(+), 15 deletions(-)
  22
  23 --- a/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c
  24 +++ b/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c
  25 @@ -1336,10 +1336,17 @@ static u32 get_colorcode(enum mipi_dsi_p
  26         return 0x005;
  27  }
  28
  29 +/* Maximum frequency for LP escape clock (20MHz), and some magic numbers */
  30 +#define RP1DSI_ESC_CLK_KHZ      20000
  31 +#define RP1DSI_TO_CLK_DIV           5
  32 +#define RP1DSI_HSTX_TO_MIN      0x200
  33 +#define RP1DSI_LPRX_TO_VAL      0x400
  34 +#define RP1DSI_BTA_TO_VAL       0xd00
  35 +
  36  void rp1dsi_dsi_setup(struct rp1_dsi *dsi, struct drm_display_mode const *mode)
  37  {
  38         u32 timeout, mask, vid_mode_cfg;
  39 -       u32 freq_khz;
  40 +       int lane_kbps;
  41         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(dsi->display_format);
  42
  43         DSI_WRITE(DSI_PHY_IF_CFG, dsi->lanes - 1);
  44 @@ -1349,28 +1356,33 @@ void rp1dsi_dsi_setup(struct rp1_dsi *ds
  45         /* a conservative guess (LP escape is slow!) */
  46         DSI_WRITE(DSI_DPI_LP_CMD_TIM, 0x00100000);
  47
  48 -       /* Drop to LP where possible */
  49 +       /* Drop to LP where possible; use LP Escape for all commands */
  50         vid_mode_cfg = 0xbf00;
  51         if (!(dsi->display_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))
  52                 vid_mode_cfg |= 0x01;
  53         if (dsi->display_flags & MIPI_DSI_MODE_VIDEO_BURST)
  54                 vid_mode_cfg |= 0x02;
  55         DSI_WRITE(DSI_VID_MODE_CFG, vid_mode_cfg);
  56 -
  57 -       /* Use LP Escape Data signalling for all commands */
  58         DSI_WRITE(DSI_CMD_MODE_CFG, 0x10F7F00);
  59 +
  60         /* Select Command Mode */
  61         DSI_WRITE(DSI_MODE_CFG, 1);
  62 -       /* XXX magic number */
  63 -       DSI_WRITE(DSI_TO_CNT_CFG, 0x02000200);
  64 -       /* XXX magic number */
  65 -       DSI_WRITE(DSI_BTA_TO_CNT, 0x800);
  66
  67 +       /* Set timeouts and clock dividers */
  68 +       DSI_WRITE(DSI_TO_CNT_CFG,
  69 +                 (max((bpp * mode->htotal) / (7 * RP1DSI_TO_CLK_DIV * dsi->lanes),
  70 +                      RP1DSI_HSTX_TO_MIN) << 16) |
  71 +                 RP1DSI_LPRX_TO_VAL);
  72 +       DSI_WRITE(DSI_BTA_TO_CNT, RP1DSI_BTA_TO_VAL);
  73 +       lane_kbps = (bpp *  mode->clock) / dsi->lanes;
  74 +       DSI_WRITE(DSI_CLKMGR_CFG,
  75 +                 (RP1DSI_TO_CLK_DIV << 8) |
  76 +                 max(2, lane_kbps / (8 * RP1DSI_ESC_CLK_KHZ) + 1));
  77 +
  78 +       /* Configure video timings */
  79         DSI_WRITE(DSI_VID_PKT_SIZE, mode->hdisplay);
  80         DSI_WRITE(DSI_VID_NUM_CHUNKS, 0);
  81         DSI_WRITE(DSI_VID_NULL_SIZE, 0);
  82 -
  83 -       /* Note, unlike Argon firmware, here we DON'T consider sync to be concurrent with porch */
  84         DSI_WRITE(DSI_VID_HSA_TIME,
  85                   (bpp * (mode->hsync_end - mode->hsync_start)) / (8 * dsi->lanes));
  86         DSI_WRITE(DSI_VID_HBP_TIME,
  87 @@ -1381,9 +1393,8 @@ void rp1dsi_dsi_setup(struct rp1_dsi *ds
  88         DSI_WRITE(DSI_VID_VFP_LINES, (mode->vsync_start - mode->vdisplay));
  89         DSI_WRITE(DSI_VID_VACTIVE_LINES, mode->vdisplay);
  90
  91 -       freq_khz = (bpp *  mode->clock) / dsi->lanes;
  92 -
  93 -       dphy_init_khz(dsi, rp1dsi_refclk_freq(dsi) / 1000, freq_khz);
  94 +       /* Init PHY */
  95 +       dphy_init_khz(dsi, rp1dsi_refclk_freq(dsi) / 1000, lane_kbps);
  96
  97         DSI_WRITE(DSI_PHY_TMR_LPCLK_CFG,
  98                   (hsfreq_table[dsi->hsfreq_index].clk_lp2hs << DSI_PHY_TMR_LP2HS_LSB) |
  99 @@ -1392,8 +1403,6 @@ void rp1dsi_dsi_setup(struct rp1_dsi *ds
 100                   (hsfreq_table[dsi->hsfreq_index].data_lp2hs << DSI_PHY_TMR_LP2HS_LSB) |
 101                   (hsfreq_table[dsi->hsfreq_index].data_hs2lp << DSI_PHY_TMR_HS2LP_LSB));
 102
 103 -       DSI_WRITE(DSI_CLKMGR_CFG, 0x00000505);
 104 -
 105         /* Wait for PLL lock */
 106         for (timeout = (1 << 14); timeout != 0; --timeout) {
 107                 usleep_range(10, 50);