git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From eab19e7bde679f56241db0c51f94f056fcffd6a9 Mon Sep 17 00:00:00 2001
   2 From: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
   3 Date: Wed, 4 Sep 2024 19:28:50 +0100
   4 Subject: [PATCH 1252/1350] drivers: drm: rp1-vec: Increase width limit, for
   5  PAL 16:9 @ 18MHz
   6
   7 There was no technical reason for the DRM mode's width limit of 848;
   8 increase it to 960 (720*18MHz/13.5MHz) to support ~square pixels on
   9 16:9 screens. Tweak the PAL active window to start slightly earlier.
  10 (The maximum number of visible columns at 18MHz is about 942.)
  11
  12 Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
  13 ---
  14  drivers/gpu/drm/rp1/rp1-vec/rp1_vec.c    | 4 ++--
  15  drivers/gpu/drm/rp1/rp1-vec/rp1_vec_hw.c | 4 ++--
  16  2 files changed, 4 insertions(+), 4 deletions(-)
  17
  18 --- a/drivers/gpu/drm/rp1/rp1-vec/rp1_vec.c
  19 +++ b/drivers/gpu/drm/rp1/rp1-vec/rp1_vec.c
  20 @@ -508,8 +508,8 @@ static int rp1vec_platform_probe(struct
  21
  22         vec->drm.mode_config.min_width  = 256;
  23         vec->drm.mode_config.min_height = 128;
  24 -       vec->drm.mode_config.max_width  = 848; /* for System E */
  25 -       vec->drm.mode_config.max_height = 738; /* for System E */
  26 +       vec->drm.mode_config.max_width  = 960; /* for "widescreen" @ 18MHz */
  27 +       vec->drm.mode_config.max_height = 738; /* for System E only */
  28         vec->drm.mode_config.preferred_depth = 32;
  29         vec->drm.mode_config.prefer_shadow = 0;
  30         vec->drm.mode_config.quirk_addfb_prefer_host_byte_order = true;
  31 --- a/drivers/gpu/drm/rp1/rp1-vec/rp1_vec_hw.c
  32 +++ b/drivers/gpu/drm/rp1/rp1-vec/rp1_vec_hw.c
  33 @@ -195,7 +195,7 @@ static const struct rp1vec_hwmode rp1vec
  34                         .misc = 0x00091c01, /* 5-tap FIR, SEQ_EN, 8 fld sync, PAL */
  35                         .nco_freq = 0x0a8262b2cc48c1d1,
  36                         .timing_regs = {
  37 -                               0x046e0cee, 0x0d8001fb, 0x025c034f, 0x00fd0b84,
  38 +                               0x04660cee, 0x0d8001fb, 0x025c034f, 0x00fd0b84,
  39                                 0x026c0270, 0x00000004, 0x00050009, 0x00070135,
  40                                 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  41                                 0x00170136, 0x00000000,
  42 @@ -218,7 +218,7 @@ static const struct rp1vec_hwmode rp1vec
  43                         .misc = 0x0009dc03, /* 5-tap FIR, SEQ_EN, 4 flds, 8 fld sync, ilace, PAL */
  44                         .nco_freq = 0x0a8262b2cc48c1d1,
  45                         .timing_regs = {
  46 -                               0x046e0cee, 0x0d8001fb, 0x025c034f, 0x00fd0b84,
  47 +                               0x04660cee, 0x0d8001fb, 0x025c034f, 0x00fd0b84,
  48                                 0x026c0270, 0x00000004, 0x00050009, 0x00070135,
  49                                 0x013f026d, 0x00060136, 0x0140026e, 0x0150026e,
  50                                 0x00180136, 0x026f0017,