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1 From acb06ebe2d1f043fd597f5c33aff048ae1804293 Mon Sep 17 00:00:00 2001
2 From: devi priya <quic_devipriy@quicinc.com>
3 Date: Thu, 1 Aug 2024 11:18:01 +0530
4 Subject: [PATCH 04/22] v6.14: arm64: dts: qcom: ipq9574: Add PCIe PHYs and
5 controller nodes
6
7 Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
8 found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3
9 host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.
10
11 Signed-off-by: devi priya <quic_devipriy@quicinc.com>
12 Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
13 Link: https://lore.kernel.org/r/20240801054803.3015572-3-quic_srichara@quicinc.com
14 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
15 ---
16 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 420 +++++++++++++++++++++++++-
17 1 file changed, 416 insertions(+), 4 deletions(-)
18
19 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
20 +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
21 @@ -226,6 +226,52 @@
22 reg = <0x00060000 0x6000>;
23 };
24
25 + pcie0_phy: phy@84000 {
26 + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
27 + reg = <0x00084000 0x1000>;
28 +
29 + clocks = <&gcc GCC_PCIE0_AUX_CLK>,
30 + <&gcc GCC_PCIE0_AHB_CLK>,
31 + <&gcc GCC_PCIE0_PIPE_CLK>;
32 + clock-names = "aux", "cfg_ahb", "pipe";
33 +
34 + assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
35 + assigned-clock-rates = <20000000>;
36 +
37 + resets = <&gcc GCC_PCIE0_PHY_BCR>,
38 + <&gcc GCC_PCIE0PHY_PHY_BCR>;
39 + reset-names = "phy", "common";
40 +
41 + #clock-cells = <0>;
42 + clock-output-names = "gcc_pcie0_pipe_clk_src";
43 +
44 + #phy-cells = <0>;
45 + status = "disabled";
46 + };
47 +
48 + pcie2_phy: phy@8c000 {
49 + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
50 + reg = <0x0008c000 0x2000>;
51 +
52 + clocks = <&gcc GCC_PCIE2_AUX_CLK>,
53 + <&gcc GCC_PCIE2_AHB_CLK>,
54 + <&gcc GCC_PCIE2_PIPE_CLK>;
55 + clock-names = "aux", "cfg_ahb", "pipe";
56 +
57 + assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
58 + assigned-clock-rates = <20000000>;
59 +
60 + resets = <&gcc GCC_PCIE2_PHY_BCR>,
61 + <&gcc GCC_PCIE2PHY_PHY_BCR>;
62 + reset-names = "phy", "common";
63 +
64 + #clock-cells = <0>;
65 + clock-output-names = "gcc_pcie2_pipe_clk_src";
66 +
67 + #phy-cells = <0>;
68 + status = "disabled";
69 + };
70 +
71 rng: rng@e3000 {
72 compatible = "qcom,prng-ee";
73 reg = <0x000e3000 0x1000>;
74 @@ -243,6 +289,52 @@
75 status = "disabled";
76 };
77
78 + pcie3_phy: phy@f4000 {
79 + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
80 + reg = <0x000f4000 0x2000>;
81 +
82 + clocks = <&gcc GCC_PCIE3_AUX_CLK>,
83 + <&gcc GCC_PCIE3_AHB_CLK>,
84 + <&gcc GCC_PCIE3_PIPE_CLK>;
85 + clock-names = "aux", "cfg_ahb", "pipe";
86 +
87 + assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
88 + assigned-clock-rates = <20000000>;
89 +
90 + resets = <&gcc GCC_PCIE3_PHY_BCR>,
91 + <&gcc GCC_PCIE3PHY_PHY_BCR>;
92 + reset-names = "phy", "common";
93 +
94 + #clock-cells = <0>;
95 + clock-output-names = "gcc_pcie3_pipe_clk_src";
96 +
97 + #phy-cells = <0>;
98 + status = "disabled";
99 + };
100 +
101 + pcie1_phy: phy@fc000 {
102 + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
103 + reg = <0x000fc000 0x1000>;
104 +
105 + clocks = <&gcc GCC_PCIE1_AUX_CLK>,
106 + <&gcc GCC_PCIE1_AHB_CLK>,
107 + <&gcc GCC_PCIE1_PIPE_CLK>;
108 + clock-names = "aux", "cfg_ahb", "pipe";
109 +
110 + assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
111 + assigned-clock-rates = <20000000>;
112 +
113 + resets = <&gcc GCC_PCIE1_PHY_BCR>,
114 + <&gcc GCC_PCIE1PHY_PHY_BCR>;
115 + reset-names = "phy", "common";
116 +
117 + #clock-cells = <0>;
118 + clock-output-names = "gcc_pcie1_pipe_clk_src";
119 +
120 + #phy-cells = <0>;
121 + status = "disabled";
122 + };
123 +
124 qfprom: efuse@a4000 {
125 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
126 reg = <0x000a4000 0x5a1>;
127 @@ -309,10 +401,10 @@
128 clocks = <&xo_board_clk>,
129 <&sleep_clk>,
130 <0>,
131 - <0>,
132 - <0>,
133 - <0>,
134 - <0>,
135 + <&pcie0_phy>,
136 + <&pcie1_phy>,
137 + <&pcie2_phy>,
138 + <&pcie3_phy>,
139 <0>;
140 #clock-cells = <1>;
141 #reset-cells = <1>;
142 @@ -756,6 +848,326 @@
143 status = "disabled";
144 };
145 };
146 +
147 + pcie1: pcie@10000000 {
148 + compatible = "qcom,pcie-ipq9574";
149 + reg = <0x10000000 0xf1d>,
150 + <0x10000f20 0xa8>,
151 + <0x10001000 0x1000>,
152 + <0x000f8000 0x4000>,
153 + <0x10100000 0x1000>;
154 + reg-names = "dbi", "elbi", "atu", "parf", "config";
155 + device_type = "pci";
156 + linux,pci-domain = <1>;
157 + bus-range = <0x00 0xff>;
158 + num-lanes = <1>;
159 + #address-cells = <3>;
160 + #size-cells = <2>;
161 +
162 + ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>,
163 + <0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>;
164 +
165 + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
166 + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
167 + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
168 + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
169 + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
170 + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
171 + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
172 + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
173 + interrupt-names = "msi0",
174 + "msi1",
175 + "msi2",
176 + "msi3",
177 + "msi4",
178 + "msi5",
179 + "msi6",
180 + "msi7";
181 +
182 + #interrupt-cells = <1>;
183 + interrupt-map-mask = <0 0 0 0x7>;
184 + interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
185 + <0 0 0 2 &intc 0 0 49 IRQ_TYPE_LEVEL_HIGH>,
186 + <0 0 0 3 &intc 0 0 84 IRQ_TYPE_LEVEL_HIGH>,
187 + <0 0 0 4 &intc 0 0 85 IRQ_TYPE_LEVEL_HIGH>;
188 +
189 + clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
190 + <&gcc GCC_PCIE1_AXI_S_CLK>,
191 + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
192 + <&gcc GCC_PCIE1_RCHNG_CLK>,
193 + <&gcc GCC_PCIE1_AHB_CLK>,
194 + <&gcc GCC_PCIE1_AUX_CLK>;
195 + clock-names = "axi_m",
196 + "axi_s",
197 + "axi_bridge",
198 + "rchng",
199 + "ahb",
200 + "aux";
201 +
202 + resets = <&gcc GCC_PCIE1_PIPE_ARES>,
203 + <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
204 + <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>,
205 + <&gcc GCC_PCIE1_AXI_S_ARES>,
206 + <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>,
207 + <&gcc GCC_PCIE1_AXI_M_ARES>,
208 + <&gcc GCC_PCIE1_AUX_ARES>,
209 + <&gcc GCC_PCIE1_AHB_ARES>;
210 + reset-names = "pipe",
211 + "sticky",
212 + "axi_s_sticky",
213 + "axi_s",
214 + "axi_m_sticky",
215 + "axi_m",
216 + "aux",
217 + "ahb";
218 +
219 + phys = <&pcie1_phy>;
220 + phy-names = "pciephy";
221 + interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
222 + <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>;
223 + interconnect-names = "pcie-mem", "cpu-pcie";
224 + status = "disabled";
225 + };
226 +
227 + pcie3: pcie@18000000 {
228 + compatible = "qcom,pcie-ipq9574";
229 + reg = <0x18000000 0xf1d>,
230 + <0x18000f20 0xa8>,
231 + <0x18001000 0x1000>,
232 + <0x000f0000 0x4000>,
233 + <0x18100000 0x1000>;
234 + reg-names = "dbi", "elbi", "atu", "parf", "config";
235 + device_type = "pci";
236 + linux,pci-domain = <3>;
237 + bus-range = <0x00 0xff>;
238 + num-lanes = <2>;
239 + #address-cells = <3>;
240 + #size-cells = <2>;
241 +
242 + ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>,
243 + <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>;
244 +
245 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
246 + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
247 + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
248 + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
249 + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
250 + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
251 + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
252 + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
253 + interrupt-names = "msi0",
254 + "msi1",
255 + "msi2",
256 + "msi3",
257 + "msi4",
258 + "msi5",
259 + "msi6",
260 + "msi7";
261 +
262 + #interrupt-cells = <1>;
263 + interrupt-map-mask = <0 0 0 0x7>;
264 + interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>,
265 + <0 0 0 2 &intc 0 0 190 IRQ_TYPE_LEVEL_HIGH>,
266 + <0 0 0 3 &intc 0 0 191 IRQ_TYPE_LEVEL_HIGH>,
267 + <0 0 0 4 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>;
268 +
269 + clocks = <&gcc GCC_PCIE3_AXI_M_CLK>,
270 + <&gcc GCC_PCIE3_AXI_S_CLK>,
271 + <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>,
272 + <&gcc GCC_PCIE3_RCHNG_CLK>,
273 + <&gcc GCC_PCIE3_AHB_CLK>,
274 + <&gcc GCC_PCIE3_AUX_CLK>;
275 + clock-names = "axi_m",
276 + "axi_s",
277 + "axi_bridge",
278 + "rchng",
279 + "ahb",
280 + "aux";
281 +
282 + resets = <&gcc GCC_PCIE3_PIPE_ARES>,
283 + <&gcc GCC_PCIE3_CORE_STICKY_ARES>,
284 + <&gcc GCC_PCIE3_AXI_S_STICKY_ARES>,
285 + <&gcc GCC_PCIE3_AXI_S_ARES>,
286 + <&gcc GCC_PCIE3_AXI_M_STICKY_ARES>,
287 + <&gcc GCC_PCIE3_AXI_M_ARES>,
288 + <&gcc GCC_PCIE3_AUX_ARES>,
289 + <&gcc GCC_PCIE3_AHB_ARES>;
290 + reset-names = "pipe",
291 + "sticky",
292 + "axi_s_sticky",
293 + "axi_s",
294 + "axi_m_sticky",
295 + "axi_m",
296 + "aux",
297 + "ahb";
298 +
299 + phys = <&pcie3_phy>;
300 + phy-names = "pciephy";
301 + interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>,
302 + <&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>;
303 + interconnect-names = "pcie-mem", "cpu-pcie";
304 + status = "disabled";
305 + };
306 +
307 + pcie2: pcie@20000000 {
308 + compatible = "qcom,pcie-ipq9574";
309 + reg = <0x20000000 0xf1d>,
310 + <0x20000f20 0xa8>,
311 + <0x20001000 0x1000>,
312 + <0x00088000 0x4000>,
313 + <0x20100000 0x1000>;
314 + reg-names = "dbi", "elbi", "atu", "parf", "config";
315 + device_type = "pci";
316 + linux,pci-domain = <2>;
317 + bus-range = <0x00 0xff>;
318 + num-lanes = <2>;
319 + #address-cells = <3>;
320 + #size-cells = <2>;
321 +
322 + ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x100000>,
323 + <0x02000000 0x0 0x20300000 0x20300000 0x0 0x7d00000>;
324 +
325 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
326 + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
327 + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
328 + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
329 + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
330 + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
331 + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
332 + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
333 + interrupt-names = "msi0",
334 + "msi1",
335 + "msi2",
336 + "msi3",
337 + "msi4",
338 + "msi5",
339 + "msi6",
340 + "msi7";
341 +
342 + #interrupt-cells = <1>;
343 + interrupt-map-mask = <0 0 0 0x7>;
344 + interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
345 + <0 0 0 2 &intc 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
346 + <0 0 0 3 &intc 0 0 186 IRQ_TYPE_LEVEL_HIGH>,
347 + <0 0 0 4 &intc 0 0 187 IRQ_TYPE_LEVEL_HIGH>;
348 +
349 + clocks = <&gcc GCC_PCIE2_AXI_M_CLK>,
350 + <&gcc GCC_PCIE2_AXI_S_CLK>,
351 + <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>,
352 + <&gcc GCC_PCIE2_RCHNG_CLK>,
353 + <&gcc GCC_PCIE2_AHB_CLK>,
354 + <&gcc GCC_PCIE2_AUX_CLK>;
355 + clock-names = "axi_m",
356 + "axi_s",
357 + "axi_bridge",
358 + "rchng",
359 + "ahb",
360 + "aux";
361 +
362 + resets = <&gcc GCC_PCIE2_PIPE_ARES>,
363 + <&gcc GCC_PCIE2_CORE_STICKY_ARES>,
364 + <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>,
365 + <&gcc GCC_PCIE2_AXI_S_ARES>,
366 + <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>,
367 + <&gcc GCC_PCIE2_AXI_M_ARES>,
368 + <&gcc GCC_PCIE2_AUX_ARES>,
369 + <&gcc GCC_PCIE2_AHB_ARES>;
370 + reset-names = "pipe",
371 + "sticky",
372 + "axi_s_sticky",
373 + "axi_s",
374 + "axi_m_sticky",
375 + "axi_m",
376 + "aux",
377 + "ahb";
378 +
379 + phys = <&pcie2_phy>;
380 + phy-names = "pciephy";
381 + interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>,
382 + <&gcc MASTER_SNOC_PCIE2 &gcc SLAVE_SNOC_PCIE2>;
383 + interconnect-names = "pcie-mem", "cpu-pcie";
384 + status = "disabled";
385 + };
386 +
387 + pcie0: pci@28000000 {
388 + compatible = "qcom,pcie-ipq9574";
389 + reg = <0x28000000 0xf1d>,
390 + <0x28000f20 0xa8>,
391 + <0x28001000 0x1000>,
392 + <0x00080000 0x4000>,
393 + <0x28100000 0x1000>;
394 + reg-names = "dbi", "elbi", "atu", "parf", "config";
395 + device_type = "pci";
396 + linux,pci-domain = <0>;
397 + bus-range = <0x00 0xff>;
398 + num-lanes = <1>;
399 + #address-cells = <3>;
400 + #size-cells = <2>;
401 +
402 + ranges = <0x01000000 0x0 0x00000000 0x28200000 0x0 0x100000>,
403 + <0x02000000 0x0 0x28300000 0x28300000 0x0 0x7d00000>;
404 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
405 + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
406 + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
407 + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
408 + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
409 + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
410 + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
411 + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
412 + interrupt-names = "msi0",
413 + "msi1",
414 + "msi2",
415 + "msi3",
416 + "msi4",
417 + "msi5",
418 + "msi6",
419 + "msi7";
420 +
421 + #interrupt-cells = <1>;
422 + interrupt-map-mask = <0 0 0 0x7>;
423 + interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>,
424 + <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>,
425 + <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>,
426 + <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>;
427 +
428 + clocks = <&gcc GCC_PCIE0_AXI_M_CLK>,
429 + <&gcc GCC_PCIE0_AXI_S_CLK>,
430 + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
431 + <&gcc GCC_PCIE0_RCHNG_CLK>,
432 + <&gcc GCC_PCIE0_AHB_CLK>,
433 + <&gcc GCC_PCIE0_AUX_CLK>;
434 + clock-names = "axi_m",
435 + "axi_s",
436 + "axi_bridge",
437 + "rchng",
438 + "ahb",
439 + "aux";
440 +
441 + resets = <&gcc GCC_PCIE0_PIPE_ARES>,
442 + <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
443 + <&gcc GCC_PCIE0_AXI_S_STICKY_ARES>,
444 + <&gcc GCC_PCIE0_AXI_S_ARES>,
445 + <&gcc GCC_PCIE0_AXI_M_STICKY_ARES>,
446 + <&gcc GCC_PCIE0_AXI_M_ARES>,
447 + <&gcc GCC_PCIE0_AUX_ARES>,
448 + <&gcc GCC_PCIE0_AHB_ARES>;
449 + reset-names = "pipe",
450 + "sticky",
451 + "axi_s_sticky",
452 + "axi_s",
453 + "axi_m_sticky",
454 + "axi_m",
455 + "aux",
456 + "ahb";
457 +
458 + phys = <&pcie0_phy>;
459 + phy-names = "pciephy";
460 + interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>,
461 + <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>;
462 + interconnect-names = "pcie-mem", "cpu-pcie";
463 + status = "disabled";
464 + };
465 +
466 };
467
468 thermal-zones {
Mirror of https://github.com/openwrt/openwrt.git