1 From f2743ae3ff84579981ac513f512b9df945d109c0 Mon Sep 17 00:00:00 2001
2 From: Chukun Pan <amadeus@jmu.edu.cn>
3 Date: Thu, 20 Jun 2024 23:01:21 +0800
4 Subject: [PATCH] clk: qcom: gcc-ipq6018: update sdcc max clock frequency
6 The mmc controller of the IPQ6018 does not support HS400 mode.
7 So adjust the maximum clock frequency of sdcc to 200 MHz (HS200).
9 Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
10 Link: https://lore.kernel.org/r/20240620150122.1406631-2-amadeus@jmu.edu.cn
11 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
13 drivers/clk/qcom/gcc-ipq6018.c | 2 +-
14 1 file changed, 1 insertion(+), 1 deletion(-)
16 --- a/drivers/clk/qcom/gcc-ipq6018.c
17 +++ b/drivers/clk/qcom/gcc-ipq6018.c
18 @@ -1617,7 +1617,7 @@ static const struct freq_tbl ftbl_sdcc_a
19 F(96000000, P_GPLL2, 12, 0, 0),
20 F(177777778, P_GPLL0, 4.5, 0, 0),
21 F(192000000, P_GPLL2, 6, 0, 0),
22 - F(384000000, P_GPLL2, 3, 0, 0),
23 + F(200000000, P_GPLL0, 4, 0, 0),