git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From 0a19b5256303d2f35be9272832b01a170c9a039b Mon Sep 17 00:00:00 2001
   2 From: Jonathan Bell <jonathan@raspberrypi.com>
   3 Date: Wed, 22 May 2024 09:46:54 +0100
   4 Subject: [PATCH 1100/1135] drivers: pcie-brcmstb: add best-effort workaround
   5  for QoS bug on bcm2712
   6
   7 If a set of read requests are issued by an endpoint, they are streamed
   8 into a resynchronisation FIFO prior to exiting the RC. This FIFO has an
   9 edge case where it can drop QoS for a request to 0 if there's a single
  10 outstanding read request in the FIFO, and another is pushed when the
  11 FIFO is popped. Requests with a QoS of 0 can take hundreds of
  12 microseconds to complete.
  13
  14 By adding an experimentally-determined amount of backpressure on the pop
  15 side, the critical level transition can largely be avoided.
  16
  17 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  18 ---
  19  drivers/pci/controller/pcie-brcmstb.c | 12 ++++++++++++
  20  1 file changed, 12 insertions(+)
  21
  22 --- a/drivers/pci/controller/pcie-brcmstb.c
  23 +++ b/drivers/pci/controller/pcie-brcmstb.c
  24 @@ -568,6 +568,18 @@ static void brcm_pcie_set_tc_qos(struct
  25                 AXI_DIS_QOS_GATING_IN_MASTER;
  26         writel(reg, pcie->base + PCIE_MISC_AXI_INTF_CTRL);
  27
  28 +       /*
  29 +        * If the QOS_UPDATE_TIMING_FIX bit is Reserved-0, then this is a
  30 +        * 2712C1 chip, or a single-lane RC. Use the best-effort alternative
  31 +        * which is to partially throttle AXI requests in-flight to the SDC.
  32 +        */
  33 +       reg = readl(pcie->base + PCIE_MISC_AXI_INTF_CTRL);
  34 +       if (!(reg & AXI_EN_QOS_UPDATE_TIMING_FIX)) {
  35 +               reg &= ~AXI_MASTER_MAX_OUTSTANDING_REQUESTS_MASK;
  36 +               reg |= 15;
  37 +               writel(reg, pcie->base + PCIE_MISC_AXI_INTF_CTRL);
  38 +       }
  39 +
  40         /* Disable VDM reception by default - QoS map defaults to 0 */
  41         reg = readl(pcie->base + PCIE_MISC_CTRL_1);
  42         reg &= ~PCIE_MISC_CTRL_1_EN_VDM_QOS_CONTROL_MASK;