git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From 326be62eaf2e89767b7b9223f88eaf3c041b98d2 Mon Sep 17 00:00:00 2001
   2 From: Sebastian Reichel <sebastian.reichel@collabora.com>
   3 Date: Fri, 26 Jan 2024 19:18:25 +0100
   4 Subject: [PATCH] clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf
   5
   6 Currently pclk_vo1grf is not exposed, but it should be referenced
   7 from the vo1_grf syscon, which needs it enabled. That syscon is
   8 required for HDMI RX and TX functionality among other things.
   9
  10 Apart from that pclk_vo0grf and pclk_vo1grf are both linked gates
  11 and need the VO's hclk enabled in addition to their parent clock.
  12
  13 No Fixes tag has been added, since the logic requiring these clocks
  14 is not yet upstream anyways.
  15
  16 Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
  17 Link: https://lore.kernel.org/r/20240126182919.48402-5-sebastian.reichel@collabora.com
  18 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  19 ---
  20  drivers/clk/rockchip/clk-rk3588.c | 10 ++++------
  21  1 file changed, 4 insertions(+), 6 deletions(-)
  22
  23 --- a/drivers/clk/rockchip/clk-rk3588.c
  24 +++ b/drivers/clk/rockchip/clk-rk3588.c
  25 @@ -1851,8 +1851,6 @@ static struct rockchip_clk_branch rk3588
  26                         RK3588_CLKGATE_CON(56), 0, GFLAGS),
  27         GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0,
  28                         RK3588_CLKGATE_CON(56), 1, GFLAGS),
  29 -       GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED,
  30 -                       RK3588_CLKGATE_CON(55), 10, GFLAGS),
  31         COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0,
  32                         RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS,
  33                         RK3588_CLKGATE_CON(56), 11, GFLAGS),
  34 @@ -1998,8 +1996,6 @@ static struct rockchip_clk_branch rk3588
  35                         RK3588_CLKGATE_CON(60), 9, GFLAGS),
  36         GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0,
  37                         RK3588_CLKGATE_CON(60), 10, GFLAGS),
  38 -       GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED,
  39 -                       RK3588_CLKGATE_CON(59), 12, GFLAGS),
  40         GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0,
  41                         RK3588_CLKGATE_CON(59), 14, GFLAGS),
  42         GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0,
  43 @@ -2447,12 +2443,14 @@ static struct rockchip_clk_branch rk3588
  44         GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
  45         GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
  46         GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
  47 -       GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS),
  48 +       GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
  49         GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
  50 -       GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS),
  51 +       GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
  52         GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
  53         GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
  54         GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
  55 +       GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", "hclk_vo0", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS),
  56 +       GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", "hclk_vo1", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
  57  };
  58
  59  static void __init rk3588_clk_init(struct device_node *np)