git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From 591da388c344f934601548cb44f54eab012c6c94 Mon Sep 17 00:00:00 2001
   2 From: Robert Marko <robimarko@gmail.com>
   3 Date: Fri, 13 Oct 2023 18:39:34 +0200
   4 Subject: [PATCH] arm64: dts: qcom: ipq8074: pass QMP PCI PHY PIPE clocks to
   5  GCC
   6
   7 Pass QMP PCI PHY PIPE clocks to the GCC controller so it does not have to
   8 find them by matching globaly by name.
   9
  10 If not passed directly, driver maintains backwards compatibility by then
  11 falling back to global lookup.
  12
  13 Signed-off-by: Robert Marko <robimarko@gmail.com>
  14 Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  15 Link: https://lore.kernel.org/r/20231013164025.3541606-2-robimarko@gmail.com
  16 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  17 ---
  18  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 ++++++++--
  19  1 file changed, 8 insertions(+), 2 deletions(-)
  20
  21 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  22 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  23 @@ -371,8 +371,14 @@
  24                 gcc: gcc@1800000 {
  25                         compatible = "qcom,gcc-ipq8074";
  26                         reg = <0x01800000 0x80000>;
  27 -                       clocks = <&xo>, <&sleep_clk>;
  28 -                       clock-names = "xo", "sleep_clk";
  29 +                       clocks = <&xo>,
  30 +                                <&sleep_clk>,
  31 +                                <&pcie_qmp0>,
  32 +                                <&pcie_qmp1>;
  33 +                       clock-names = "xo",
  34 +                                     "sleep_clk",
  35 +                                     "pcie0_pipe",
  36 +                                     "pcie1_pipe";
  37                         #clock-cells = <1>;
  38                         #power-domain-cells = <1>;
  39                         #reset-cells = <1>;