git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From 62307c5e153de617cb0827509fb964df051caaac Mon Sep 17 00:00:00 2001
   2 From: Luo Jie <quic_luoj@quicinc.com>
   3 Date: Fri, 3 Jan 2025 15:31:38 +0800
   4 Subject: [PATCH 09/22] v6.14: arm64: dts: qcom: ipq9574: Update xo_board_clk
   5  to use fixed factor clock
   6
   7 xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output clock
   8 48 MHZ (also being the reference clock of CMN PLL) divided 2 by analog
   9 block routing channel.
  10
  11 Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
  12 Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
  13 Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-5-c89fb4d4849d@quicinc.com
  14 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  15 ---
  16  arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 7 ++++++-
  17  arch/arm64/boot/dts/qcom/ipq9574.dtsi            | 3 ++-
  18  2 files changed, 8 insertions(+), 2 deletions(-)
  19
  20 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
  21 +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
  22 @@ -175,8 +175,13 @@
  23         clock-mult = <1>;
  24  };
  25
  26 +/*
  27 + * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed
  28 + * from WiFi output clock 48 MHZ divided by 2.
  29 + */
  30  &xo_board_clk {
  31 -       clock-frequency = <24000000>;
  32 +       clock-div = <2>;
  33 +       clock-mult = <1>;
  34  };
  35
  36  &xo_clk {
  37 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
  38 +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
  39 @@ -32,7 +32,8 @@
  40                 };
  41
  42                 xo_board_clk: xo-board-clk {
  43 -                       compatible = "fixed-clock";
  44 +                       compatible = "fixed-factor-clock";
  45 +                       clocks = <&ref_48mhz_clk>;
  46                         #clock-cells = <0>;
  47                 };
  48