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1 From 1416a9b2ba710d31954131c06d46f298e340aa2c Mon Sep 17 00:00:00 2001
2 From: Heiner Kallweit <hkallweit1@gmail.com>
3 Date: Sat, 11 Jan 2025 21:50:19 +0100
4 Subject: [PATCH] net: phy: move realtek PHY driver to its own subdirectory
5
6 In preparation of adding a source file with hwmon support, move the
7 Realtek PHY driver to its own subdirectory and rename realtek.c to
8 realtek_main.c.
9
10 Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
11 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
12 Link: https://patch.msgid.link/c566551b-c915-4e34-9b33-129a6ddd6e4c@gmail.com
13 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
14 ---
15 drivers/net/phy/Kconfig | 5 +----
16 drivers/net/phy/Makefile | 2 +-
17 drivers/net/phy/realtek/Kconfig | 5 +++++
18 drivers/net/phy/realtek/Makefile | 3 +++
19 drivers/net/phy/{realtek.c => realtek/realtek_main.c} | 0
20 5 files changed, 10 insertions(+), 5 deletions(-)
21 create mode 100644 drivers/net/phy/realtek/Kconfig
22 create mode 100644 drivers/net/phy/realtek/Makefile
23 rename drivers/net/phy/{realtek.c => realtek/realtek_main.c} (100%)
24
25 --- a/drivers/net/phy/Kconfig
26 +++ b/drivers/net/phy/Kconfig
27 @@ -325,10 +325,7 @@ config QSEMI_PHY
28 help
29 Currently supports the qs6612
30
31 -config REALTEK_PHY
32 - tristate "Realtek PHYs"
33 - help
34 - Supports the Realtek 821x PHY.
35 +source "drivers/net/phy/realtek/Kconfig"
36
37 config RENESAS_PHY
38 tristate "Renesas PHYs"
39 --- a/drivers/net/phy/Makefile
40 +++ b/drivers/net/phy/Makefile
41 @@ -83,7 +83,7 @@ obj-$(CONFIG_NXP_CBTX_PHY) += nxp-cbtx.o
42 obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
43 obj-y += qcom/
44 obj-$(CONFIG_QSEMI_PHY) += qsemi.o
45 -obj-$(CONFIG_REALTEK_PHY) += realtek.o
46 +obj-$(CONFIG_REALTEK_PHY) += realtek/
47 obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
48 obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o
49 obj-$(CONFIG_SMSC_PHY) += smsc.o
50 --- /dev/null
51 +++ b/drivers/net/phy/realtek/Kconfig
52 @@ -0,0 +1,5 @@
53 +# SPDX-License-Identifier: GPL-2.0-only
54 +config REALTEK_PHY
55 + tristate "Realtek PHYs"
56 + help
57 + Currently supports RTL821x/RTL822x and fast ethernet PHYs
58 --- /dev/null
59 +++ b/drivers/net/phy/realtek/Makefile
60 @@ -0,0 +1,3 @@
61 +# SPDX-License-Identifier: GPL-2.0
62 +realtek-y += realtek_main.o
63 +obj-$(CONFIG_REALTEK_PHY) += realtek.o
64 --- a/drivers/net/phy/realtek.c
65 +++ /dev/null
66 @@ -1,1589 +0,0 @@
67 -// SPDX-License-Identifier: GPL-2.0+
68 -/* drivers/net/phy/realtek.c
69 - *
70 - * Driver for Realtek PHYs
71 - *
72 - * Author: Johnson Leung <r58129@freescale.com>
73 - *
74 - * Copyright (c) 2004 Freescale Semiconductor, Inc.
75 - */
76 -#include <linux/bitops.h>
77 -#include <linux/of.h>
78 -#include <linux/phy.h>
79 -#include <linux/module.h>
80 -#include <linux/delay.h>
81 -#include <linux/clk.h>
82 -
83 -#define RTL821x_PHYSR 0x11
84 -#define RTL821x_PHYSR_DUPLEX BIT(13)
85 -#define RTL821x_PHYSR_SPEED GENMASK(15, 14)
86 -
87 -#define RTL821x_INER 0x12
88 -#define RTL8211B_INER_INIT 0x6400
89 -#define RTL8211E_INER_LINK_STATUS BIT(10)
90 -#define RTL8211F_INER_LINK_STATUS BIT(4)
91 -
92 -#define RTL821x_INSR 0x13
93 -
94 -#define RTL821x_EXT_PAGE_SELECT 0x1e
95 -#define RTL821x_PAGE_SELECT 0x1f
96 -
97 -#define RTL8211F_PHYCR1 0x18
98 -#define RTL8211F_PHYCR2 0x19
99 -#define RTL8211F_INSR 0x1d
100 -
101 -#define RTL8211F_LEDCR 0x10
102 -#define RTL8211F_LEDCR_MODE BIT(15)
103 -#define RTL8211F_LEDCR_ACT_TXRX BIT(4)
104 -#define RTL8211F_LEDCR_LINK_1000 BIT(3)
105 -#define RTL8211F_LEDCR_LINK_100 BIT(1)
106 -#define RTL8211F_LEDCR_LINK_10 BIT(0)
107 -#define RTL8211F_LEDCR_MASK GENMASK(4, 0)
108 -#define RTL8211F_LEDCR_SHIFT 5
109 -
110 -#define RTL8211F_TX_DELAY BIT(8)
111 -#define RTL8211F_RX_DELAY BIT(3)
112 -
113 -#define RTL8211F_ALDPS_PLL_OFF BIT(1)
114 -#define RTL8211F_ALDPS_ENABLE BIT(2)
115 -#define RTL8211F_ALDPS_XTAL_OFF BIT(12)
116 -
117 -#define RTL8211E_CTRL_DELAY BIT(13)
118 -#define RTL8211E_TX_DELAY BIT(12)
119 -#define RTL8211E_RX_DELAY BIT(11)
120 -
121 -#define RTL8211F_CLKOUT_EN BIT(0)
122 -
123 -#define RTL8201F_ISR 0x1e
124 -#define RTL8201F_ISR_ANERR BIT(15)
125 -#define RTL8201F_ISR_DUPLEX BIT(13)
126 -#define RTL8201F_ISR_LINK BIT(11)
127 -#define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \
128 - RTL8201F_ISR_DUPLEX | \
129 - RTL8201F_ISR_LINK)
130 -#define RTL8201F_IER 0x13
131 -
132 -#define RTL822X_VND1_SERDES_OPTION 0x697a
133 -#define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0)
134 -#define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0
135 -#define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2
136 -
137 -#define RTL822X_VND1_SERDES_CTRL3 0x7580
138 -#define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0)
139 -#define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02
140 -#define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16
141 -
142 -/* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
143 - * is set, they cannot be accessed by C45-over-C22.
144 - */
145 -#define RTL822X_VND2_GBCR 0xa412
146 -
147 -#define RTL822X_VND2_GANLPAR 0xa414
148 -
149 -#define RTL8366RB_POWER_SAVE 0x15
150 -#define RTL8366RB_POWER_SAVE_ON BIT(12)
151 -
152 -#define RTL9000A_GINMR 0x14
153 -#define RTL9000A_GINMR_LINK_STATUS BIT(4)
154 -
155 -#define RTL_VND2_PHYSR 0xa434
156 -#define RTL_VND2_PHYSR_DUPLEX BIT(3)
157 -#define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4)
158 -#define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9)
159 -#define RTL_VND2_PHYSR_MASTER BIT(11)
160 -#define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH)
161 -
162 -#define RTL_GENERIC_PHYID 0x001cc800
163 -#define RTL_8211FVD_PHYID 0x001cc878
164 -#define RTL_8221B 0x001cc840
165 -#define RTL_8221B_VB_CG 0x001cc849
166 -#define RTL_8221B_VN_CG 0x001cc84a
167 -#define RTL_8251B 0x001cc862
168 -
169 -#define RTL8211F_LED_COUNT 3
170 -
171 -MODULE_DESCRIPTION("Realtek PHY driver");
172 -MODULE_AUTHOR("Johnson Leung");
173 -MODULE_LICENSE("GPL");
174 -
175 -struct rtl821x_priv {
176 - u16 phycr1;
177 - u16 phycr2;
178 - bool has_phycr2;
179 - struct clk *clk;
180 -};
181 -
182 -static int rtl821x_read_page(struct phy_device *phydev)
183 -{
184 - return __phy_read(phydev, RTL821x_PAGE_SELECT);
185 -}
186 -
187 -static int rtl821x_write_page(struct phy_device *phydev, int page)
188 -{
189 - return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
190 -}
191 -
192 -static int rtl821x_probe(struct phy_device *phydev)
193 -{
194 - struct device *dev = &phydev->mdio.dev;
195 - struct rtl821x_priv *priv;
196 - u32 phy_id = phydev->drv->phy_id;
197 - int ret;
198 -
199 - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
200 - if (!priv)
201 - return -ENOMEM;
202 -
203 - priv->clk = devm_clk_get_optional_enabled(dev, NULL);
204 - if (IS_ERR(priv->clk))
205 - return dev_err_probe(dev, PTR_ERR(priv->clk),
206 - "failed to get phy clock\n");
207 -
208 - ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
209 - if (ret < 0)
210 - return ret;
211 -
212 - priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF);
213 - if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
214 - priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF;
215 -
216 - priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
217 - if (priv->has_phycr2) {
218 - ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
219 - if (ret < 0)
220 - return ret;
221 -
222 - priv->phycr2 = ret & RTL8211F_CLKOUT_EN;
223 - if (of_property_read_bool(dev->of_node, "realtek,clkout-disable"))
224 - priv->phycr2 &= ~RTL8211F_CLKOUT_EN;
225 - }
226 -
227 - phydev->priv = priv;
228 -
229 - return 0;
230 -}
231 -
232 -static int rtl8201_ack_interrupt(struct phy_device *phydev)
233 -{
234 - int err;
235 -
236 - err = phy_read(phydev, RTL8201F_ISR);
237 -
238 - return (err < 0) ? err : 0;
239 -}
240 -
241 -static int rtl821x_ack_interrupt(struct phy_device *phydev)
242 -{
243 - int err;
244 -
245 - err = phy_read(phydev, RTL821x_INSR);
246 -
247 - return (err < 0) ? err : 0;
248 -}
249 -
250 -static int rtl8211f_ack_interrupt(struct phy_device *phydev)
251 -{
252 - int err;
253 -
254 - err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
255 -
256 - return (err < 0) ? err : 0;
257 -}
258 -
259 -static int rtl8201_config_intr(struct phy_device *phydev)
260 -{
261 - u16 val;
262 - int err;
263 -
264 - if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
265 - err = rtl8201_ack_interrupt(phydev);
266 - if (err)
267 - return err;
268 -
269 - val = BIT(13) | BIT(12) | BIT(11);
270 - err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
271 - } else {
272 - val = 0;
273 - err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
274 - if (err)
275 - return err;
276 -
277 - err = rtl8201_ack_interrupt(phydev);
278 - }
279 -
280 - return err;
281 -}
282 -
283 -static int rtl8211b_config_intr(struct phy_device *phydev)
284 -{
285 - int err;
286 -
287 - if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
288 - err = rtl821x_ack_interrupt(phydev);
289 - if (err)
290 - return err;
291 -
292 - err = phy_write(phydev, RTL821x_INER,
293 - RTL8211B_INER_INIT);
294 - } else {
295 - err = phy_write(phydev, RTL821x_INER, 0);
296 - if (err)
297 - return err;
298 -
299 - err = rtl821x_ack_interrupt(phydev);
300 - }
301 -
302 - return err;
303 -}
304 -
305 -static int rtl8211e_config_intr(struct phy_device *phydev)
306 -{
307 - int err;
308 -
309 - if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
310 - err = rtl821x_ack_interrupt(phydev);
311 - if (err)
312 - return err;
313 -
314 - err = phy_write(phydev, RTL821x_INER,
315 - RTL8211E_INER_LINK_STATUS);
316 - } else {
317 - err = phy_write(phydev, RTL821x_INER, 0);
318 - if (err)
319 - return err;
320 -
321 - err = rtl821x_ack_interrupt(phydev);
322 - }
323 -
324 - return err;
325 -}
326 -
327 -static int rtl8211f_config_intr(struct phy_device *phydev)
328 -{
329 - u16 val;
330 - int err;
331 -
332 - if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
333 - err = rtl8211f_ack_interrupt(phydev);
334 - if (err)
335 - return err;
336 -
337 - val = RTL8211F_INER_LINK_STATUS;
338 - err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
339 - } else {
340 - val = 0;
341 - err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
342 - if (err)
343 - return err;
344 -
345 - err = rtl8211f_ack_interrupt(phydev);
346 - }
347 -
348 - return err;
349 -}
350 -
351 -static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
352 -{
353 - int irq_status;
354 -
355 - irq_status = phy_read(phydev, RTL8201F_ISR);
356 - if (irq_status < 0) {
357 - phy_error(phydev);
358 - return IRQ_NONE;
359 - }
360 -
361 - if (!(irq_status & RTL8201F_ISR_MASK))
362 - return IRQ_NONE;
363 -
364 - phy_trigger_machine(phydev);
365 -
366 - return IRQ_HANDLED;
367 -}
368 -
369 -static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
370 -{
371 - int irq_status, irq_enabled;
372 -
373 - irq_status = phy_read(phydev, RTL821x_INSR);
374 - if (irq_status < 0) {
375 - phy_error(phydev);
376 - return IRQ_NONE;
377 - }
378 -
379 - irq_enabled = phy_read(phydev, RTL821x_INER);
380 - if (irq_enabled < 0) {
381 - phy_error(phydev);
382 - return IRQ_NONE;
383 - }
384 -
385 - if (!(irq_status & irq_enabled))
386 - return IRQ_NONE;
387 -
388 - phy_trigger_machine(phydev);
389 -
390 - return IRQ_HANDLED;
391 -}
392 -
393 -static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
394 -{
395 - int irq_status;
396 -
397 - irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
398 - if (irq_status < 0) {
399 - phy_error(phydev);
400 - return IRQ_NONE;
401 - }
402 -
403 - if (!(irq_status & RTL8211F_INER_LINK_STATUS))
404 - return IRQ_NONE;
405 -
406 - phy_trigger_machine(phydev);
407 -
408 - return IRQ_HANDLED;
409 -}
410 -
411 -static int rtl8211_config_aneg(struct phy_device *phydev)
412 -{
413 - int ret;
414 -
415 - ret = genphy_config_aneg(phydev);
416 - if (ret < 0)
417 - return ret;
418 -
419 - /* Quirk was copied from vendor driver. Unfortunately it includes no
420 - * description of the magic numbers.
421 - */
422 - if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
423 - phy_write(phydev, 0x17, 0x2138);
424 - phy_write(phydev, 0x0e, 0x0260);
425 - } else {
426 - phy_write(phydev, 0x17, 0x2108);
427 - phy_write(phydev, 0x0e, 0x0000);
428 - }
429 -
430 - return 0;
431 -}
432 -
433 -static int rtl8211c_config_init(struct phy_device *phydev)
434 -{
435 - /* RTL8211C has an issue when operating in Gigabit slave mode */
436 - return phy_set_bits(phydev, MII_CTRL1000,
437 - CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
438 -}
439 -
440 -static int rtl8211f_config_init(struct phy_device *phydev)
441 -{
442 - struct rtl821x_priv *priv = phydev->priv;
443 - struct device *dev = &phydev->mdio.dev;
444 - u16 val_txdly, val_rxdly;
445 - int ret;
446 -
447 - ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
448 - RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
449 - priv->phycr1);
450 - if (ret < 0) {
451 - dev_err(dev, "aldps mode configuration failed: %pe\n",
452 - ERR_PTR(ret));
453 - return ret;
454 - }
455 -
456 - switch (phydev->interface) {
457 - case PHY_INTERFACE_MODE_RGMII:
458 - val_txdly = 0;
459 - val_rxdly = 0;
460 - break;
461 -
462 - case PHY_INTERFACE_MODE_RGMII_RXID:
463 - val_txdly = 0;
464 - val_rxdly = RTL8211F_RX_DELAY;
465 - break;
466 -
467 - case PHY_INTERFACE_MODE_RGMII_TXID:
468 - val_txdly = RTL8211F_TX_DELAY;
469 - val_rxdly = 0;
470 - break;
471 -
472 - case PHY_INTERFACE_MODE_RGMII_ID:
473 - val_txdly = RTL8211F_TX_DELAY;
474 - val_rxdly = RTL8211F_RX_DELAY;
475 - break;
476 -
477 - default: /* the rest of the modes imply leaving delay as is. */
478 - return 0;
479 - }
480 -
481 - ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
482 - val_txdly);
483 - if (ret < 0) {
484 - dev_err(dev, "Failed to update the TX delay register\n");
485 - return ret;
486 - } else if (ret) {
487 - dev_dbg(dev,
488 - "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
489 - val_txdly ? "Enabling" : "Disabling");
490 - } else {
491 - dev_dbg(dev,
492 - "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
493 - val_txdly ? "enabled" : "disabled");
494 - }
495 -
496 - ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
497 - val_rxdly);
498 - if (ret < 0) {
499 - dev_err(dev, "Failed to update the RX delay register\n");
500 - return ret;
501 - } else if (ret) {
502 - dev_dbg(dev,
503 - "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
504 - val_rxdly ? "Enabling" : "Disabling");
505 - } else {
506 - dev_dbg(dev,
507 - "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
508 - val_rxdly ? "enabled" : "disabled");
509 - }
510 -
511 - if (priv->has_phycr2) {
512 - ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
513 - RTL8211F_CLKOUT_EN, priv->phycr2);
514 - if (ret < 0) {
515 - dev_err(dev, "clkout configuration failed: %pe\n",
516 - ERR_PTR(ret));
517 - return ret;
518 - }
519 -
520 - return genphy_soft_reset(phydev);
521 - }
522 -
523 - return 0;
524 -}
525 -
526 -static int rtl821x_suspend(struct phy_device *phydev)
527 -{
528 - struct rtl821x_priv *priv = phydev->priv;
529 - int ret = 0;
530 -
531 - if (!phydev->wol_enabled) {
532 - ret = genphy_suspend(phydev);
533 -
534 - if (ret)
535 - return ret;
536 -
537 - clk_disable_unprepare(priv->clk);
538 - }
539 -
540 - return ret;
541 -}
542 -
543 -static int rtl821x_resume(struct phy_device *phydev)
544 -{
545 - struct rtl821x_priv *priv = phydev->priv;
546 - int ret;
547 -
548 - if (!phydev->wol_enabled)
549 - clk_prepare_enable(priv->clk);
550 -
551 - ret = genphy_resume(phydev);
552 - if (ret < 0)
553 - return ret;
554 -
555 - msleep(20);
556 -
557 - return 0;
558 -}
559 -
560 -static int rtl8211f_led_hw_is_supported(struct phy_device *phydev, u8 index,
561 - unsigned long rules)
562 -{
563 - const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) |
564 - BIT(TRIGGER_NETDEV_LINK_100) |
565 - BIT(TRIGGER_NETDEV_LINK_1000) |
566 - BIT(TRIGGER_NETDEV_RX) |
567 - BIT(TRIGGER_NETDEV_TX);
568 -
569 - /* The RTL8211F PHY supports these LED settings on up to three LEDs:
570 - * - Link: Configurable subset of 10/100/1000 link rates
571 - * - Active: Blink on activity, RX or TX is not differentiated
572 - * The Active option has two modes, A and B:
573 - * - A: Link and Active indication at configurable, but matching,
574 - * subset of 10/100/1000 link rates
575 - * - B: Link indication at configurable subset of 10/100/1000 link
576 - * rates and Active indication always at all three 10+100+1000
577 - * link rates.
578 - * This code currently uses mode B only.
579 - */
580 -
581 - if (index >= RTL8211F_LED_COUNT)
582 - return -EINVAL;
583 -
584 - /* Filter out any other unsupported triggers. */
585 - if (rules & ~mask)
586 - return -EOPNOTSUPP;
587 -
588 - /* RX and TX are not differentiated, either both are set or not set. */
589 - if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX)))
590 - return -EOPNOTSUPP;
591 -
592 - return 0;
593 -}
594 -
595 -static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index,
596 - unsigned long *rules)
597 -{
598 - int val;
599 -
600 - if (index >= RTL8211F_LED_COUNT)
601 - return -EINVAL;
602 -
603 - val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR);
604 - if (val < 0)
605 - return val;
606 -
607 - val >>= RTL8211F_LEDCR_SHIFT * index;
608 - val &= RTL8211F_LEDCR_MASK;
609 -
610 - if (val & RTL8211F_LEDCR_LINK_10)
611 - set_bit(TRIGGER_NETDEV_LINK_10, rules);
612 -
613 - if (val & RTL8211F_LEDCR_LINK_100)
614 - set_bit(TRIGGER_NETDEV_LINK_100, rules);
615 -
616 - if (val & RTL8211F_LEDCR_LINK_1000)
617 - set_bit(TRIGGER_NETDEV_LINK_1000, rules);
618 -
619 - if (val & RTL8211F_LEDCR_ACT_TXRX) {
620 - set_bit(TRIGGER_NETDEV_RX, rules);
621 - set_bit(TRIGGER_NETDEV_TX, rules);
622 - }
623 -
624 - return 0;
625 -}
626 -
627 -static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index,
628 - unsigned long rules)
629 -{
630 - const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index);
631 - u16 reg = 0;
632 -
633 - if (index >= RTL8211F_LED_COUNT)
634 - return -EINVAL;
635 -
636 - if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
637 - reg |= RTL8211F_LEDCR_LINK_10;
638 -
639 - if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
640 - reg |= RTL8211F_LEDCR_LINK_100;
641 -
642 - if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
643 - reg |= RTL8211F_LEDCR_LINK_1000;
644 -
645 - if (test_bit(TRIGGER_NETDEV_RX, &rules) ||
646 - test_bit(TRIGGER_NETDEV_TX, &rules)) {
647 - reg |= RTL8211F_LEDCR_ACT_TXRX;
648 - }
649 -
650 - reg <<= RTL8211F_LEDCR_SHIFT * index;
651 - reg |= RTL8211F_LEDCR_MODE; /* Mode B */
652 -
653 - return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg);
654 -}
655 -
656 -static int rtl8211e_config_init(struct phy_device *phydev)
657 -{
658 - int ret = 0, oldpage;
659 - u16 val;
660 -
661 - /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
662 - switch (phydev->interface) {
663 - case PHY_INTERFACE_MODE_RGMII:
664 - val = RTL8211E_CTRL_DELAY | 0;
665 - break;
666 - case PHY_INTERFACE_MODE_RGMII_ID:
667 - val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
668 - break;
669 - case PHY_INTERFACE_MODE_RGMII_RXID:
670 - val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
671 - break;
672 - case PHY_INTERFACE_MODE_RGMII_TXID:
673 - val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
674 - break;
675 - default: /* the rest of the modes imply leaving delays as is. */
676 - return 0;
677 - }
678 -
679 - /* According to a sample driver there is a 0x1c config register on the
680 - * 0xa4 extension page (0x7) layout. It can be used to disable/enable
681 - * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
682 - * The configuration register definition:
683 - * 14 = reserved
684 - * 13 = Force Tx RX Delay controlled by bit12 bit11,
685 - * 12 = RX Delay, 11 = TX Delay
686 - * 10:0 = Test && debug settings reserved by realtek
687 - */
688 - oldpage = phy_select_page(phydev, 0x7);
689 - if (oldpage < 0)
690 - goto err_restore_page;
691 -
692 - ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
693 - if (ret)
694 - goto err_restore_page;
695 -
696 - ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
697 - | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
698 - val);
699 -
700 -err_restore_page:
701 - return phy_restore_page(phydev, oldpage, ret);
702 -}
703 -
704 -static int rtl8211b_suspend(struct phy_device *phydev)
705 -{
706 - phy_write(phydev, MII_MMD_DATA, BIT(9));
707 -
708 - return genphy_suspend(phydev);
709 -}
710 -
711 -static int rtl8211b_resume(struct phy_device *phydev)
712 -{
713 - phy_write(phydev, MII_MMD_DATA, 0);
714 -
715 - return genphy_resume(phydev);
716 -}
717 -
718 -static int rtl8366rb_config_init(struct phy_device *phydev)
719 -{
720 - int ret;
721 -
722 - ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
723 - RTL8366RB_POWER_SAVE_ON);
724 - if (ret) {
725 - dev_err(&phydev->mdio.dev,
726 - "error enabling power management\n");
727 - }
728 -
729 - return ret;
730 -}
731 -
732 -/* get actual speed to cover the downshift case */
733 -static void rtlgen_decode_physr(struct phy_device *phydev, int val)
734 -{
735 - /* bit 3
736 - * 0: Half Duplex
737 - * 1: Full Duplex
738 - */
739 - if (val & RTL_VND2_PHYSR_DUPLEX)
740 - phydev->duplex = DUPLEX_FULL;
741 - else
742 - phydev->duplex = DUPLEX_HALF;
743 -
744 - switch (val & RTL_VND2_PHYSR_SPEED_MASK) {
745 - case 0x0000:
746 - phydev->speed = SPEED_10;
747 - break;
748 - case 0x0010:
749 - phydev->speed = SPEED_100;
750 - break;
751 - case 0x0020:
752 - phydev->speed = SPEED_1000;
753 - break;
754 - case 0x0200:
755 - phydev->speed = SPEED_10000;
756 - break;
757 - case 0x0210:
758 - phydev->speed = SPEED_2500;
759 - break;
760 - case 0x0220:
761 - phydev->speed = SPEED_5000;
762 - break;
763 - default:
764 - break;
765 - }
766 -
767 - /* bit 11
768 - * 0: Slave Mode
769 - * 1: Master Mode
770 - */
771 - if (phydev->speed >= 1000) {
772 - if (val & RTL_VND2_PHYSR_MASTER)
773 - phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
774 - else
775 - phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
776 - } else {
777 - phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
778 - }
779 -}
780 -
781 -static int rtlgen_read_status(struct phy_device *phydev)
782 -{
783 - int ret, val;
784 -
785 - ret = genphy_read_status(phydev);
786 - if (ret < 0)
787 - return ret;
788 -
789 - if (!phydev->link)
790 - return 0;
791 -
792 - val = phy_read_paged(phydev, 0xa43, 0x12);
793 - if (val < 0)
794 - return val;
795 -
796 - rtlgen_decode_physr(phydev, val);
797 -
798 - return 0;
799 -}
800 -
801 -static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
802 -{
803 - int ret;
804 -
805 - if (devnum == MDIO_MMD_VEND2) {
806 - rtl821x_write_page(phydev, regnum >> 4);
807 - ret = __phy_read(phydev, 0x10 + ((regnum & 0xf) >> 1));
808 - rtl821x_write_page(phydev, 0);
809 - } else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
810 - rtl821x_write_page(phydev, 0xa5c);
811 - ret = __phy_read(phydev, 0x12);
812 - rtl821x_write_page(phydev, 0);
813 - } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
814 - rtl821x_write_page(phydev, 0xa5d);
815 - ret = __phy_read(phydev, 0x10);
816 - rtl821x_write_page(phydev, 0);
817 - } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
818 - rtl821x_write_page(phydev, 0xa5d);
819 - ret = __phy_read(phydev, 0x11);
820 - rtl821x_write_page(phydev, 0);
821 - } else {
822 - ret = -EOPNOTSUPP;
823 - }
824 -
825 - return ret;
826 -}
827 -
828 -static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
829 - u16 val)
830 -{
831 - int ret;
832 -
833 - if (devnum == MDIO_MMD_VEND2) {
834 - rtl821x_write_page(phydev, regnum >> 4);
835 - ret = __phy_write(phydev, 0x10 + ((regnum & 0xf) >> 1), val);
836 - rtl821x_write_page(phydev, 0);
837 - } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
838 - rtl821x_write_page(phydev, 0xa5d);
839 - ret = __phy_write(phydev, 0x10, val);
840 - rtl821x_write_page(phydev, 0);
841 - } else {
842 - ret = -EOPNOTSUPP;
843 - }
844 -
845 - return ret;
846 -}
847 -
848 -static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
849 -{
850 - int ret = rtlgen_read_mmd(phydev, devnum, regnum);
851 -
852 - if (ret != -EOPNOTSUPP)
853 - return ret;
854 -
855 - if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
856 - rtl821x_write_page(phydev, 0xa6e);
857 - ret = __phy_read(phydev, 0x16);
858 - rtl821x_write_page(phydev, 0);
859 - } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
860 - rtl821x_write_page(phydev, 0xa6d);
861 - ret = __phy_read(phydev, 0x12);
862 - rtl821x_write_page(phydev, 0);
863 - } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
864 - rtl821x_write_page(phydev, 0xa6d);
865 - ret = __phy_read(phydev, 0x10);
866 - rtl821x_write_page(phydev, 0);
867 - }
868 -
869 - return ret;
870 -}
871 -
872 -static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
873 - u16 val)
874 -{
875 - int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
876 -
877 - if (ret != -EOPNOTSUPP)
878 - return ret;
879 -
880 - if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
881 - rtl821x_write_page(phydev, 0xa6d);
882 - ret = __phy_write(phydev, 0x12, val);
883 - rtl821x_write_page(phydev, 0);
884 - }
885 -
886 - return ret;
887 -}
888 -
889 -static int rtl822xb_config_init(struct phy_device *phydev)
890 -{
891 - bool has_2500, has_sgmii;
892 - u16 mode;
893 - int ret;
894 -
895 - has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX,
896 - phydev->host_interfaces) ||
897 - phydev->interface == PHY_INTERFACE_MODE_2500BASEX;
898 -
899 - has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII,
900 - phydev->host_interfaces) ||
901 - phydev->interface == PHY_INTERFACE_MODE_SGMII;
902 -
903 - /* fill in possible interfaces */
904 - __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces,
905 - has_2500);
906 - __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces,
907 - has_sgmii);
908 -
909 - if (!has_2500 && !has_sgmii)
910 - return 0;
911 -
912 - /* determine SerDes option mode */
913 - if (has_2500 && !has_sgmii) {
914 - mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX;
915 - phydev->rate_matching = RATE_MATCH_PAUSE;
916 - } else {
917 - mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII;
918 - phydev->rate_matching = RATE_MATCH_NONE;
919 - }
920 -
921 - /* the following sequence with magic numbers sets up the SerDes
922 - * option mode
923 - */
924 - ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0);
925 - if (ret < 0)
926 - return ret;
927 -
928 - ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1,
929 - RTL822X_VND1_SERDES_OPTION,
930 - RTL822X_VND1_SERDES_OPTION_MODE_MASK,
931 - mode);
932 - if (ret < 0)
933 - return ret;
934 -
935 - ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503);
936 - if (ret < 0)
937 - return ret;
938 -
939 - ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455);
940 - if (ret < 0)
941 - return ret;
942 -
943 - return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020);
944 -}
945 -
946 -static int rtl822xb_get_rate_matching(struct phy_device *phydev,
947 - phy_interface_t iface)
948 -{
949 - int val;
950 -
951 - /* Only rate matching at 2500base-x */
952 - if (iface != PHY_INTERFACE_MODE_2500BASEX)
953 - return RATE_MATCH_NONE;
954 -
955 - val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION);
956 - if (val < 0)
957 - return val;
958 -
959 - if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) ==
960 - RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX)
961 - return RATE_MATCH_PAUSE;
962 -
963 - /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */
964 - return RATE_MATCH_NONE;
965 -}
966 -
967 -static int rtl822x_get_features(struct phy_device *phydev)
968 -{
969 - int val;
970 -
971 - val = phy_read_paged(phydev, 0xa61, 0x13);
972 - if (val < 0)
973 - return val;
974 -
975 - linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
976 - phydev->supported, val & MDIO_PMA_SPEED_2_5G);
977 - linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
978 - phydev->supported, val & MDIO_PMA_SPEED_5G);
979 - linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
980 - phydev->supported, val & MDIO_SPEED_10G);
981 -
982 - return genphy_read_abilities(phydev);
983 -}
984 -
985 -static int rtl822x_config_aneg(struct phy_device *phydev)
986 -{
987 - int ret = 0;
988 -
989 - if (phydev->autoneg == AUTONEG_ENABLE) {
990 - u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
991 -
992 - ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
993 - MDIO_AN_10GBT_CTRL_ADV2_5G |
994 - MDIO_AN_10GBT_CTRL_ADV5G,
995 - adv);
996 - if (ret < 0)
997 - return ret;
998 - }
999 -
1000 - return __genphy_config_aneg(phydev, ret);
1001 -}
1002 -
1003 -static void rtl822xb_update_interface(struct phy_device *phydev)
1004 -{
1005 - int val;
1006 -
1007 - if (!phydev->link)
1008 - return;
1009 -
1010 - /* Change interface according to serdes mode */
1011 - val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3);
1012 - if (val < 0)
1013 - return;
1014 -
1015 - switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) {
1016 - case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX:
1017 - phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
1018 - break;
1019 - case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII:
1020 - phydev->interface = PHY_INTERFACE_MODE_SGMII;
1021 - break;
1022 - }
1023 -}
1024 -
1025 -static int rtl822x_read_status(struct phy_device *phydev)
1026 -{
1027 - int lpadv, ret;
1028 -
1029 - mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
1030 -
1031 - ret = rtlgen_read_status(phydev);
1032 - if (ret < 0)
1033 - return ret;
1034 -
1035 - if (phydev->autoneg == AUTONEG_DISABLE ||
1036 - !phydev->autoneg_complete)
1037 - return 0;
1038 -
1039 - lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
1040 - if (lpadv < 0)
1041 - return lpadv;
1042 -
1043 - mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv);
1044 -
1045 - return 0;
1046 -}
1047 -
1048 -static int rtl822xb_read_status(struct phy_device *phydev)
1049 -{
1050 - int ret;
1051 -
1052 - ret = rtl822x_read_status(phydev);
1053 - if (ret < 0)
1054 - return ret;
1055 -
1056 - rtl822xb_update_interface(phydev);
1057 -
1058 - return 0;
1059 -}
1060 -
1061 -static int rtl822x_c45_get_features(struct phy_device *phydev)
1062 -{
1063 - linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
1064 - phydev->supported);
1065 -
1066 - return genphy_c45_pma_read_abilities(phydev);
1067 -}
1068 -
1069 -static int rtl822x_c45_config_aneg(struct phy_device *phydev)
1070 -{
1071 - bool changed = false;
1072 - int ret, val;
1073 -
1074 - if (phydev->autoneg == AUTONEG_DISABLE)
1075 - return genphy_c45_pma_setup_forced(phydev);
1076 -
1077 - ret = genphy_c45_an_config_aneg(phydev);
1078 - if (ret < 0)
1079 - return ret;
1080 - if (ret > 0)
1081 - changed = true;
1082 -
1083 - val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
1084 -
1085 - /* Vendor register as C45 has no standardized support for 1000BaseT */
1086 - ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL822X_VND2_GBCR,
1087 - ADVERTISE_1000FULL, val);
1088 - if (ret < 0)
1089 - return ret;
1090 - if (ret > 0)
1091 - changed = true;
1092 -
1093 - return genphy_c45_check_and_restart_aneg(phydev, changed);
1094 -}
1095 -
1096 -static int rtl822x_c45_read_status(struct phy_device *phydev)
1097 -{
1098 - int ret, val;
1099 -
1100 - /* Vendor register as C45 has no standardized support for 1000BaseT */
1101 - if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) {
1102 - val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1103 - RTL822X_VND2_GANLPAR);
1104 - if (val < 0)
1105 - return val;
1106 - } else {
1107 - val = 0;
1108 - }
1109 - mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
1110 -
1111 - ret = genphy_c45_read_status(phydev);
1112 - if (ret < 0)
1113 - return ret;
1114 -
1115 - if (!phydev->link) {
1116 - phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1117 - return 0;
1118 - }
1119 -
1120 - /* Read actual speed from vendor register. */
1121 - val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR);
1122 - if (val < 0)
1123 - return val;
1124 -
1125 - rtlgen_decode_physr(phydev, val);
1126 -
1127 - return 0;
1128 -}
1129 -
1130 -static int rtl822xb_c45_read_status(struct phy_device *phydev)
1131 -{
1132 - int ret;
1133 -
1134 - ret = rtl822x_c45_read_status(phydev);
1135 - if (ret < 0)
1136 - return ret;
1137 -
1138 - rtl822xb_update_interface(phydev);
1139 -
1140 - return 0;
1141 -}
1142 -
1143 -static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
1144 -{
1145 - int val;
1146 -
1147 - phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
1148 - val = phy_read(phydev, 0x13);
1149 - phy_write(phydev, RTL821x_PAGE_SELECT, 0);
1150 -
1151 - return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
1152 -}
1153 -
1154 -/* On internal PHY's MMD reads over C22 always return 0.
1155 - * Check a MMD register which is known to be non-zero.
1156 - */
1157 -static bool rtlgen_supports_mmd(struct phy_device *phydev)
1158 -{
1159 - int val;
1160 -
1161 - phy_lock_mdio_bus(phydev);
1162 - __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS);
1163 - __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE);
1164 - __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR);
1165 - val = __phy_read(phydev, MII_MMD_DATA);
1166 - phy_unlock_mdio_bus(phydev);
1167 -
1168 - return val > 0;
1169 -}
1170 -
1171 -static int rtlgen_match_phy_device(struct phy_device *phydev)
1172 -{
1173 - return phydev->phy_id == RTL_GENERIC_PHYID &&
1174 - !rtlgen_supports_2_5gbps(phydev);
1175 -}
1176 -
1177 -static int rtl8226_match_phy_device(struct phy_device *phydev)
1178 -{
1179 - return phydev->phy_id == RTL_GENERIC_PHYID &&
1180 - rtlgen_supports_2_5gbps(phydev) &&
1181 - rtlgen_supports_mmd(phydev);
1182 -}
1183 -
1184 -static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
1185 - bool is_c45)
1186 -{
1187 - if (phydev->is_c45)
1188 - return is_c45 && (id == phydev->c45_ids.device_ids[1]);
1189 - else
1190 - return !is_c45 && (id == phydev->phy_id);
1191 -}
1192 -
1193 -static int rtl8221b_match_phy_device(struct phy_device *phydev)
1194 -{
1195 - return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev);
1196 -}
1197 -
1198 -static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev)
1199 -{
1200 - return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);
1201 -}
1202 -
1203 -static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev)
1204 -{
1205 - return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true);
1206 -}
1207 -
1208 -static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev)
1209 -{
1210 - return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false);
1211 -}
1212 -
1213 -static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev)
1214 -{
1215 - return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true);
1216 -}
1217 -
1218 -static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev)
1219 -{
1220 - if (phydev->is_c45)
1221 - return false;
1222 -
1223 - switch (phydev->phy_id) {
1224 - case RTL_GENERIC_PHYID:
1225 - case RTL_8221B:
1226 - case RTL_8251B:
1227 - case 0x001cc841:
1228 - break;
1229 - default:
1230 - return false;
1231 - }
1232 -
1233 - return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev);
1234 -}
1235 -
1236 -static int rtl8251b_c45_match_phy_device(struct phy_device *phydev)
1237 -{
1238 - return rtlgen_is_c45_match(phydev, RTL_8251B, true);
1239 -}
1240 -
1241 -static int rtlgen_resume(struct phy_device *phydev)
1242 -{
1243 - int ret = genphy_resume(phydev);
1244 -
1245 - /* Internal PHY's from RTL8168h up may not be instantly ready */
1246 - msleep(20);
1247 -
1248 - return ret;
1249 -}
1250 -
1251 -static int rtlgen_c45_resume(struct phy_device *phydev)
1252 -{
1253 - int ret = genphy_c45_pma_resume(phydev);
1254 -
1255 - msleep(20);
1256 -
1257 - return ret;
1258 -}
1259 -
1260 -static int rtl9000a_config_init(struct phy_device *phydev)
1261 -{
1262 - phydev->autoneg = AUTONEG_DISABLE;
1263 - phydev->speed = SPEED_100;
1264 - phydev->duplex = DUPLEX_FULL;
1265 -
1266 - return 0;
1267 -}
1268 -
1269 -static int rtl9000a_config_aneg(struct phy_device *phydev)
1270 -{
1271 - int ret;
1272 - u16 ctl = 0;
1273 -
1274 - switch (phydev->master_slave_set) {
1275 - case MASTER_SLAVE_CFG_MASTER_FORCE:
1276 - ctl |= CTL1000_AS_MASTER;
1277 - break;
1278 - case MASTER_SLAVE_CFG_SLAVE_FORCE:
1279 - break;
1280 - case MASTER_SLAVE_CFG_UNKNOWN:
1281 - case MASTER_SLAVE_CFG_UNSUPPORTED:
1282 - return 0;
1283 - default:
1284 - phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1285 - return -EOPNOTSUPP;
1286 - }
1287 -
1288 - ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
1289 - if (ret == 1)
1290 - ret = genphy_soft_reset(phydev);
1291 -
1292 - return ret;
1293 -}
1294 -
1295 -static int rtl9000a_read_status(struct phy_device *phydev)
1296 -{
1297 - int ret;
1298 -
1299 - phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
1300 - phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1301 -
1302 - ret = genphy_update_link(phydev);
1303 - if (ret)
1304 - return ret;
1305 -
1306 - ret = phy_read(phydev, MII_CTRL1000);
1307 - if (ret < 0)
1308 - return ret;
1309 - if (ret & CTL1000_AS_MASTER)
1310 - phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
1311 - else
1312 - phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
1313 -
1314 - ret = phy_read(phydev, MII_STAT1000);
1315 - if (ret < 0)
1316 - return ret;
1317 - if (ret & LPA_1000MSRES)
1318 - phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
1319 - else
1320 - phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
1321 -
1322 - return 0;
1323 -}
1324 -
1325 -static int rtl9000a_ack_interrupt(struct phy_device *phydev)
1326 -{
1327 - int err;
1328 -
1329 - err = phy_read(phydev, RTL8211F_INSR);
1330 -
1331 - return (err < 0) ? err : 0;
1332 -}
1333 -
1334 -static int rtl9000a_config_intr(struct phy_device *phydev)
1335 -{
1336 - u16 val;
1337 - int err;
1338 -
1339 - if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1340 - err = rtl9000a_ack_interrupt(phydev);
1341 - if (err)
1342 - return err;
1343 -
1344 - val = (u16)~RTL9000A_GINMR_LINK_STATUS;
1345 - err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1346 - } else {
1347 - val = ~0;
1348 - err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1349 - if (err)
1350 - return err;
1351 -
1352 - err = rtl9000a_ack_interrupt(phydev);
1353 - }
1354 -
1355 - return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1356 -}
1357 -
1358 -static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
1359 -{
1360 - int irq_status;
1361 -
1362 - irq_status = phy_read(phydev, RTL8211F_INSR);
1363 - if (irq_status < 0) {
1364 - phy_error(phydev);
1365 - return IRQ_NONE;
1366 - }
1367 -
1368 - if (!(irq_status & RTL8211F_INER_LINK_STATUS))
1369 - return IRQ_NONE;
1370 -
1371 - phy_trigger_machine(phydev);
1372 -
1373 - return IRQ_HANDLED;
1374 -}
1375 -
1376 -static struct phy_driver realtek_drvs[] = {
1377 - {
1378 - PHY_ID_MATCH_EXACT(0x00008201),
1379 - .name = "RTL8201CP Ethernet",
1380 - .read_page = rtl821x_read_page,
1381 - .write_page = rtl821x_write_page,
1382 - }, {
1383 - PHY_ID_MATCH_EXACT(0x001cc816),
1384 - .name = "RTL8201F Fast Ethernet",
1385 - .config_intr = &rtl8201_config_intr,
1386 - .handle_interrupt = rtl8201_handle_interrupt,
1387 - .suspend = genphy_suspend,
1388 - .resume = genphy_resume,
1389 - .read_page = rtl821x_read_page,
1390 - .write_page = rtl821x_write_page,
1391 - }, {
1392 - PHY_ID_MATCH_MODEL(0x001cc880),
1393 - .name = "RTL8208 Fast Ethernet",
1394 - .read_mmd = genphy_read_mmd_unsupported,
1395 - .write_mmd = genphy_write_mmd_unsupported,
1396 - .suspend = genphy_suspend,
1397 - .resume = genphy_resume,
1398 - .read_page = rtl821x_read_page,
1399 - .write_page = rtl821x_write_page,
1400 - }, {
1401 - PHY_ID_MATCH_EXACT(0x001cc910),
1402 - .name = "RTL8211 Gigabit Ethernet",
1403 - .config_aneg = rtl8211_config_aneg,
1404 - .read_mmd = &genphy_read_mmd_unsupported,
1405 - .write_mmd = &genphy_write_mmd_unsupported,
1406 - .read_page = rtl821x_read_page,
1407 - .write_page = rtl821x_write_page,
1408 - }, {
1409 - PHY_ID_MATCH_EXACT(0x001cc912),
1410 - .name = "RTL8211B Gigabit Ethernet",
1411 - .config_intr = &rtl8211b_config_intr,
1412 - .handle_interrupt = rtl821x_handle_interrupt,
1413 - .read_mmd = &genphy_read_mmd_unsupported,
1414 - .write_mmd = &genphy_write_mmd_unsupported,
1415 - .suspend = rtl8211b_suspend,
1416 - .resume = rtl8211b_resume,
1417 - .read_page = rtl821x_read_page,
1418 - .write_page = rtl821x_write_page,
1419 - }, {
1420 - PHY_ID_MATCH_EXACT(0x001cc913),
1421 - .name = "RTL8211C Gigabit Ethernet",
1422 - .config_init = rtl8211c_config_init,
1423 - .read_mmd = &genphy_read_mmd_unsupported,
1424 - .write_mmd = &genphy_write_mmd_unsupported,
1425 - .read_page = rtl821x_read_page,
1426 - .write_page = rtl821x_write_page,
1427 - }, {
1428 - PHY_ID_MATCH_EXACT(0x001cc914),
1429 - .name = "RTL8211DN Gigabit Ethernet",
1430 - .config_intr = rtl8211e_config_intr,
1431 - .handle_interrupt = rtl821x_handle_interrupt,
1432 - .suspend = genphy_suspend,
1433 - .resume = genphy_resume,
1434 - .read_page = rtl821x_read_page,
1435 - .write_page = rtl821x_write_page,
1436 - }, {
1437 - PHY_ID_MATCH_EXACT(0x001cc915),
1438 - .name = "RTL8211E Gigabit Ethernet",
1439 - .config_init = &rtl8211e_config_init,
1440 - .config_intr = &rtl8211e_config_intr,
1441 - .handle_interrupt = rtl821x_handle_interrupt,
1442 - .suspend = genphy_suspend,
1443 - .resume = genphy_resume,
1444 - .read_page = rtl821x_read_page,
1445 - .write_page = rtl821x_write_page,
1446 - }, {
1447 - PHY_ID_MATCH_EXACT(0x001cc916),
1448 - .name = "RTL8211F Gigabit Ethernet",
1449 - .probe = rtl821x_probe,
1450 - .config_init = &rtl8211f_config_init,
1451 - .read_status = rtlgen_read_status,
1452 - .config_intr = &rtl8211f_config_intr,
1453 - .handle_interrupt = rtl8211f_handle_interrupt,
1454 - .suspend = rtl821x_suspend,
1455 - .resume = rtl821x_resume,
1456 - .read_page = rtl821x_read_page,
1457 - .write_page = rtl821x_write_page,
1458 - .flags = PHY_ALWAYS_CALL_SUSPEND,
1459 - .led_hw_is_supported = rtl8211f_led_hw_is_supported,
1460 - .led_hw_control_get = rtl8211f_led_hw_control_get,
1461 - .led_hw_control_set = rtl8211f_led_hw_control_set,
1462 - }, {
1463 - PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID),
1464 - .name = "RTL8211F-VD Gigabit Ethernet",
1465 - .probe = rtl821x_probe,
1466 - .config_init = &rtl8211f_config_init,
1467 - .read_status = rtlgen_read_status,
1468 - .config_intr = &rtl8211f_config_intr,
1469 - .handle_interrupt = rtl8211f_handle_interrupt,
1470 - .suspend = rtl821x_suspend,
1471 - .resume = rtl821x_resume,
1472 - .read_page = rtl821x_read_page,
1473 - .write_page = rtl821x_write_page,
1474 - .flags = PHY_ALWAYS_CALL_SUSPEND,
1475 - }, {
1476 - .name = "Generic FE-GE Realtek PHY",
1477 - .match_phy_device = rtlgen_match_phy_device,
1478 - .read_status = rtlgen_read_status,
1479 - .suspend = genphy_suspend,
1480 - .resume = rtlgen_resume,
1481 - .read_page = rtl821x_read_page,
1482 - .write_page = rtl821x_write_page,
1483 - .read_mmd = rtlgen_read_mmd,
1484 - .write_mmd = rtlgen_write_mmd,
1485 - }, {
1486 - .name = "RTL8226 2.5Gbps PHY",
1487 - .match_phy_device = rtl8226_match_phy_device,
1488 - .get_features = rtl822x_get_features,
1489 - .config_aneg = rtl822x_config_aneg,
1490 - .read_status = rtl822x_read_status,
1491 - .suspend = genphy_suspend,
1492 - .resume = rtlgen_resume,
1493 - .read_page = rtl821x_read_page,
1494 - .write_page = rtl821x_write_page,
1495 - }, {
1496 - .match_phy_device = rtl8221b_match_phy_device,
1497 - .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
1498 - .get_features = rtl822x_get_features,
1499 - .config_aneg = rtl822x_config_aneg,
1500 - .config_init = rtl822xb_config_init,
1501 - .get_rate_matching = rtl822xb_get_rate_matching,
1502 - .read_status = rtl822xb_read_status,
1503 - .suspend = genphy_suspend,
1504 - .resume = rtlgen_resume,
1505 - .read_page = rtl821x_read_page,
1506 - .write_page = rtl821x_write_page,
1507 - }, {
1508 - PHY_ID_MATCH_EXACT(0x001cc838),
1509 - .name = "RTL8226-CG 2.5Gbps PHY",
1510 - .get_features = rtl822x_get_features,
1511 - .config_aneg = rtl822x_config_aneg,
1512 - .read_status = rtl822x_read_status,
1513 - .suspend = genphy_suspend,
1514 - .resume = rtlgen_resume,
1515 - .read_page = rtl821x_read_page,
1516 - .write_page = rtl821x_write_page,
1517 - }, {
1518 - PHY_ID_MATCH_EXACT(0x001cc848),
1519 - .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1520 - .get_features = rtl822x_get_features,
1521 - .config_aneg = rtl822x_config_aneg,
1522 - .config_init = rtl822xb_config_init,
1523 - .get_rate_matching = rtl822xb_get_rate_matching,
1524 - .read_status = rtl822xb_read_status,
1525 - .suspend = genphy_suspend,
1526 - .resume = rtlgen_resume,
1527 - .read_page = rtl821x_read_page,
1528 - .write_page = rtl821x_write_page,
1529 - }, {
1530 - .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
1531 - .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
1532 - .get_features = rtl822x_get_features,
1533 - .config_aneg = rtl822x_config_aneg,
1534 - .config_init = rtl822xb_config_init,
1535 - .get_rate_matching = rtl822xb_get_rate_matching,
1536 - .read_status = rtl822xb_read_status,
1537 - .suspend = genphy_suspend,
1538 - .resume = rtlgen_resume,
1539 - .read_page = rtl821x_read_page,
1540 - .write_page = rtl821x_write_page,
1541 - }, {
1542 - .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
1543 - .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
1544 - .config_init = rtl822xb_config_init,
1545 - .get_rate_matching = rtl822xb_get_rate_matching,
1546 - .get_features = rtl822x_c45_get_features,
1547 - .config_aneg = rtl822x_c45_config_aneg,
1548 - .read_status = rtl822xb_c45_read_status,
1549 - .suspend = genphy_c45_pma_suspend,
1550 - .resume = rtlgen_c45_resume,
1551 - }, {
1552 - .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device,
1553 - .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
1554 - .get_features = rtl822x_get_features,
1555 - .config_aneg = rtl822x_config_aneg,
1556 - .config_init = rtl822xb_config_init,
1557 - .get_rate_matching = rtl822xb_get_rate_matching,
1558 - .read_status = rtl822xb_read_status,
1559 - .suspend = genphy_suspend,
1560 - .resume = rtlgen_resume,
1561 - .read_page = rtl821x_read_page,
1562 - .write_page = rtl821x_write_page,
1563 - }, {
1564 - .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device,
1565 - .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",
1566 - .config_init = rtl822xb_config_init,
1567 - .get_rate_matching = rtl822xb_get_rate_matching,
1568 - .get_features = rtl822x_c45_get_features,
1569 - .config_aneg = rtl822x_c45_config_aneg,
1570 - .read_status = rtl822xb_c45_read_status,
1571 - .suspend = genphy_c45_pma_suspend,
1572 - .resume = rtlgen_c45_resume,
1573 - }, {
1574 - .match_phy_device = rtl8251b_c45_match_phy_device,
1575 - .name = "RTL8251B 5Gbps PHY",
1576 - .get_features = rtl822x_get_features,
1577 - .config_aneg = rtl822x_config_aneg,
1578 - .read_status = rtl822x_read_status,
1579 - .suspend = genphy_suspend,
1580 - .resume = rtlgen_resume,
1581 - .read_page = rtl821x_read_page,
1582 - .write_page = rtl821x_write_page,
1583 - }, {
1584 - .match_phy_device = rtl_internal_nbaset_match_phy_device,
1585 - .name = "Realtek Internal NBASE-T PHY",
1586 - .flags = PHY_IS_INTERNAL,
1587 - .get_features = rtl822x_get_features,
1588 - .config_aneg = rtl822x_config_aneg,
1589 - .read_status = rtl822x_read_status,
1590 - .suspend = genphy_suspend,
1591 - .resume = rtlgen_resume,
1592 - .read_page = rtl821x_read_page,
1593 - .write_page = rtl821x_write_page,
1594 - .read_mmd = rtl822x_read_mmd,
1595 - .write_mmd = rtl822x_write_mmd,
1596 - }, {
1597 - PHY_ID_MATCH_EXACT(0x001ccad0),
1598 - .name = "RTL8224 2.5Gbps PHY",
1599 - .get_features = rtl822x_c45_get_features,
1600 - .config_aneg = rtl822x_c45_config_aneg,
1601 - .read_status = rtl822x_c45_read_status,
1602 - .suspend = genphy_c45_pma_suspend,
1603 - .resume = rtlgen_c45_resume,
1604 - }, {
1605 - PHY_ID_MATCH_EXACT(0x001cc961),
1606 - .name = "RTL8366RB Gigabit Ethernet",
1607 - .config_init = &rtl8366rb_config_init,
1608 - /* These interrupts are handled by the irq controller
1609 - * embedded inside the RTL8366RB, they get unmasked when the
1610 - * irq is requested and ACKed by reading the status register,
1611 - * which is done by the irqchip code.
1612 - */
1613 - .config_intr = genphy_no_config_intr,
1614 - .handle_interrupt = genphy_handle_interrupt_no_ack,
1615 - .suspend = genphy_suspend,
1616 - .resume = genphy_resume,
1617 - }, {
1618 - PHY_ID_MATCH_EXACT(0x001ccb00),
1619 - .name = "RTL9000AA_RTL9000AN Ethernet",
1620 - .features = PHY_BASIC_T1_FEATURES,
1621 - .config_init = rtl9000a_config_init,
1622 - .config_aneg = rtl9000a_config_aneg,
1623 - .read_status = rtl9000a_read_status,
1624 - .config_intr = rtl9000a_config_intr,
1625 - .handle_interrupt = rtl9000a_handle_interrupt,
1626 - .suspend = genphy_suspend,
1627 - .resume = genphy_resume,
1628 - .read_page = rtl821x_read_page,
1629 - .write_page = rtl821x_write_page,
1630 - }, {
1631 - PHY_ID_MATCH_EXACT(0x001cc942),
1632 - .name = "RTL8365MB-VC Gigabit Ethernet",
1633 - /* Interrupt handling analogous to RTL8366RB */
1634 - .config_intr = genphy_no_config_intr,
1635 - .handle_interrupt = genphy_handle_interrupt_no_ack,
1636 - .suspend = genphy_suspend,
1637 - .resume = genphy_resume,
1638 - }, {
1639 - PHY_ID_MATCH_EXACT(0x001cc960),
1640 - .name = "RTL8366S Gigabit Ethernet",
1641 - .suspend = genphy_suspend,
1642 - .resume = genphy_resume,
1643 - .read_mmd = genphy_read_mmd_unsupported,
1644 - .write_mmd = genphy_write_mmd_unsupported,
1645 - },
1646 -};
1647 -
1648 -module_phy_driver(realtek_drvs);
1649 -
1650 -static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
1651 - { PHY_ID_MATCH_VENDOR(0x001cc800) },
1652 - { }
1653 -};
1654 -
1655 -MODULE_DEVICE_TABLE(mdio, realtek_tbl);
1656 --- /dev/null
1657 +++ b/drivers/net/phy/realtek/realtek_main.c
1658 @@ -0,0 +1,1589 @@
1659 +// SPDX-License-Identifier: GPL-2.0+
1660 +/* drivers/net/phy/realtek.c
1661 + *
1662 + * Driver for Realtek PHYs
1663 + *
1664 + * Author: Johnson Leung <r58129@freescale.com>
1665 + *
1666 + * Copyright (c) 2004 Freescale Semiconductor, Inc.
1667 + */
1668 +#include <linux/bitops.h>
1669 +#include <linux/of.h>
1670 +#include <linux/phy.h>
1671 +#include <linux/module.h>
1672 +#include <linux/delay.h>
1673 +#include <linux/clk.h>
1674 +
1675 +#define RTL821x_PHYSR 0x11
1676 +#define RTL821x_PHYSR_DUPLEX BIT(13)
1677 +#define RTL821x_PHYSR_SPEED GENMASK(15, 14)
1678 +
1679 +#define RTL821x_INER 0x12
1680 +#define RTL8211B_INER_INIT 0x6400
1681 +#define RTL8211E_INER_LINK_STATUS BIT(10)
1682 +#define RTL8211F_INER_LINK_STATUS BIT(4)
1683 +
1684 +#define RTL821x_INSR 0x13
1685 +
1686 +#define RTL821x_EXT_PAGE_SELECT 0x1e
1687 +#define RTL821x_PAGE_SELECT 0x1f
1688 +
1689 +#define RTL8211F_PHYCR1 0x18
1690 +#define RTL8211F_PHYCR2 0x19
1691 +#define RTL8211F_INSR 0x1d
1692 +
1693 +#define RTL8211F_LEDCR 0x10
1694 +#define RTL8211F_LEDCR_MODE BIT(15)
1695 +#define RTL8211F_LEDCR_ACT_TXRX BIT(4)
1696 +#define RTL8211F_LEDCR_LINK_1000 BIT(3)
1697 +#define RTL8211F_LEDCR_LINK_100 BIT(1)
1698 +#define RTL8211F_LEDCR_LINK_10 BIT(0)
1699 +#define RTL8211F_LEDCR_MASK GENMASK(4, 0)
1700 +#define RTL8211F_LEDCR_SHIFT 5
1701 +
1702 +#define RTL8211F_TX_DELAY BIT(8)
1703 +#define RTL8211F_RX_DELAY BIT(3)
1704 +
1705 +#define RTL8211F_ALDPS_PLL_OFF BIT(1)
1706 +#define RTL8211F_ALDPS_ENABLE BIT(2)
1707 +#define RTL8211F_ALDPS_XTAL_OFF BIT(12)
1708 +
1709 +#define RTL8211E_CTRL_DELAY BIT(13)
1710 +#define RTL8211E_TX_DELAY BIT(12)
1711 +#define RTL8211E_RX_DELAY BIT(11)
1712 +
1713 +#define RTL8211F_CLKOUT_EN BIT(0)
1714 +
1715 +#define RTL8201F_ISR 0x1e
1716 +#define RTL8201F_ISR_ANERR BIT(15)
1717 +#define RTL8201F_ISR_DUPLEX BIT(13)
1718 +#define RTL8201F_ISR_LINK BIT(11)
1719 +#define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \
1720 + RTL8201F_ISR_DUPLEX | \
1721 + RTL8201F_ISR_LINK)
1722 +#define RTL8201F_IER 0x13
1723 +
1724 +#define RTL822X_VND1_SERDES_OPTION 0x697a
1725 +#define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0)
1726 +#define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0
1727 +#define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2
1728 +
1729 +#define RTL822X_VND1_SERDES_CTRL3 0x7580
1730 +#define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0)
1731 +#define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02
1732 +#define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16
1733 +
1734 +/* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
1735 + * is set, they cannot be accessed by C45-over-C22.
1736 + */
1737 +#define RTL822X_VND2_GBCR 0xa412
1738 +
1739 +#define RTL822X_VND2_GANLPAR 0xa414
1740 +
1741 +#define RTL8366RB_POWER_SAVE 0x15
1742 +#define RTL8366RB_POWER_SAVE_ON BIT(12)
1743 +
1744 +#define RTL9000A_GINMR 0x14
1745 +#define RTL9000A_GINMR_LINK_STATUS BIT(4)
1746 +
1747 +#define RTL_VND2_PHYSR 0xa434
1748 +#define RTL_VND2_PHYSR_DUPLEX BIT(3)
1749 +#define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4)
1750 +#define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9)
1751 +#define RTL_VND2_PHYSR_MASTER BIT(11)
1752 +#define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH)
1753 +
1754 +#define RTL_GENERIC_PHYID 0x001cc800
1755 +#define RTL_8211FVD_PHYID 0x001cc878
1756 +#define RTL_8221B 0x001cc840
1757 +#define RTL_8221B_VB_CG 0x001cc849
1758 +#define RTL_8221B_VN_CG 0x001cc84a
1759 +#define RTL_8251B 0x001cc862
1760 +
1761 +#define RTL8211F_LED_COUNT 3
1762 +
1763 +MODULE_DESCRIPTION("Realtek PHY driver");
1764 +MODULE_AUTHOR("Johnson Leung");
1765 +MODULE_LICENSE("GPL");
1766 +
1767 +struct rtl821x_priv {
1768 + u16 phycr1;
1769 + u16 phycr2;
1770 + bool has_phycr2;
1771 + struct clk *clk;
1772 +};
1773 +
1774 +static int rtl821x_read_page(struct phy_device *phydev)
1775 +{
1776 + return __phy_read(phydev, RTL821x_PAGE_SELECT);
1777 +}
1778 +
1779 +static int rtl821x_write_page(struct phy_device *phydev, int page)
1780 +{
1781 + return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
1782 +}
1783 +
1784 +static int rtl821x_probe(struct phy_device *phydev)
1785 +{
1786 + struct device *dev = &phydev->mdio.dev;
1787 + struct rtl821x_priv *priv;
1788 + u32 phy_id = phydev->drv->phy_id;
1789 + int ret;
1790 +
1791 + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1792 + if (!priv)
1793 + return -ENOMEM;
1794 +
1795 + priv->clk = devm_clk_get_optional_enabled(dev, NULL);
1796 + if (IS_ERR(priv->clk))
1797 + return dev_err_probe(dev, PTR_ERR(priv->clk),
1798 + "failed to get phy clock\n");
1799 +
1800 + ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
1801 + if (ret < 0)
1802 + return ret;
1803 +
1804 + priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF);
1805 + if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
1806 + priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF;
1807 +
1808 + priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
1809 + if (priv->has_phycr2) {
1810 + ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
1811 + if (ret < 0)
1812 + return ret;
1813 +
1814 + priv->phycr2 = ret & RTL8211F_CLKOUT_EN;
1815 + if (of_property_read_bool(dev->of_node, "realtek,clkout-disable"))
1816 + priv->phycr2 &= ~RTL8211F_CLKOUT_EN;
1817 + }
1818 +
1819 + phydev->priv = priv;
1820 +
1821 + return 0;
1822 +}
1823 +
1824 +static int rtl8201_ack_interrupt(struct phy_device *phydev)
1825 +{
1826 + int err;
1827 +
1828 + err = phy_read(phydev, RTL8201F_ISR);
1829 +
1830 + return (err < 0) ? err : 0;
1831 +}
1832 +
1833 +static int rtl821x_ack_interrupt(struct phy_device *phydev)
1834 +{
1835 + int err;
1836 +
1837 + err = phy_read(phydev, RTL821x_INSR);
1838 +
1839 + return (err < 0) ? err : 0;
1840 +}
1841 +
1842 +static int rtl8211f_ack_interrupt(struct phy_device *phydev)
1843 +{
1844 + int err;
1845 +
1846 + err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
1847 +
1848 + return (err < 0) ? err : 0;
1849 +}
1850 +
1851 +static int rtl8201_config_intr(struct phy_device *phydev)
1852 +{
1853 + u16 val;
1854 + int err;
1855 +
1856 + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1857 + err = rtl8201_ack_interrupt(phydev);
1858 + if (err)
1859 + return err;
1860 +
1861 + val = BIT(13) | BIT(12) | BIT(11);
1862 + err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
1863 + } else {
1864 + val = 0;
1865 + err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
1866 + if (err)
1867 + return err;
1868 +
1869 + err = rtl8201_ack_interrupt(phydev);
1870 + }
1871 +
1872 + return err;
1873 +}
1874 +
1875 +static int rtl8211b_config_intr(struct phy_device *phydev)
1876 +{
1877 + int err;
1878 +
1879 + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1880 + err = rtl821x_ack_interrupt(phydev);
1881 + if (err)
1882 + return err;
1883 +
1884 + err = phy_write(phydev, RTL821x_INER,
1885 + RTL8211B_INER_INIT);
1886 + } else {
1887 + err = phy_write(phydev, RTL821x_INER, 0);
1888 + if (err)
1889 + return err;
1890 +
1891 + err = rtl821x_ack_interrupt(phydev);
1892 + }
1893 +
1894 + return err;
1895 +}
1896 +
1897 +static int rtl8211e_config_intr(struct phy_device *phydev)
1898 +{
1899 + int err;
1900 +
1901 + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1902 + err = rtl821x_ack_interrupt(phydev);
1903 + if (err)
1904 + return err;
1905 +
1906 + err = phy_write(phydev, RTL821x_INER,
1907 + RTL8211E_INER_LINK_STATUS);
1908 + } else {
1909 + err = phy_write(phydev, RTL821x_INER, 0);
1910 + if (err)
1911 + return err;
1912 +
1913 + err = rtl821x_ack_interrupt(phydev);
1914 + }
1915 +
1916 + return err;
1917 +}
1918 +
1919 +static int rtl8211f_config_intr(struct phy_device *phydev)
1920 +{
1921 + u16 val;
1922 + int err;
1923 +
1924 + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1925 + err = rtl8211f_ack_interrupt(phydev);
1926 + if (err)
1927 + return err;
1928 +
1929 + val = RTL8211F_INER_LINK_STATUS;
1930 + err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
1931 + } else {
1932 + val = 0;
1933 + err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
1934 + if (err)
1935 + return err;
1936 +
1937 + err = rtl8211f_ack_interrupt(phydev);
1938 + }
1939 +
1940 + return err;
1941 +}
1942 +
1943 +static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
1944 +{
1945 + int irq_status;
1946 +
1947 + irq_status = phy_read(phydev, RTL8201F_ISR);
1948 + if (irq_status < 0) {
1949 + phy_error(phydev);
1950 + return IRQ_NONE;
1951 + }
1952 +
1953 + if (!(irq_status & RTL8201F_ISR_MASK))
1954 + return IRQ_NONE;
1955 +
1956 + phy_trigger_machine(phydev);
1957 +
1958 + return IRQ_HANDLED;
1959 +}
1960 +
1961 +static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
1962 +{
1963 + int irq_status, irq_enabled;
1964 +
1965 + irq_status = phy_read(phydev, RTL821x_INSR);
1966 + if (irq_status < 0) {
1967 + phy_error(phydev);
1968 + return IRQ_NONE;
1969 + }
1970 +
1971 + irq_enabled = phy_read(phydev, RTL821x_INER);
1972 + if (irq_enabled < 0) {
1973 + phy_error(phydev);
1974 + return IRQ_NONE;
1975 + }
1976 +
1977 + if (!(irq_status & irq_enabled))
1978 + return IRQ_NONE;
1979 +
1980 + phy_trigger_machine(phydev);
1981 +
1982 + return IRQ_HANDLED;
1983 +}
1984 +
1985 +static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
1986 +{
1987 + int irq_status;
1988 +
1989 + irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
1990 + if (irq_status < 0) {
1991 + phy_error(phydev);
1992 + return IRQ_NONE;
1993 + }
1994 +
1995 + if (!(irq_status & RTL8211F_INER_LINK_STATUS))
1996 + return IRQ_NONE;
1997 +
1998 + phy_trigger_machine(phydev);
1999 +
2000 + return IRQ_HANDLED;
2001 +}
2002 +
2003 +static int rtl8211_config_aneg(struct phy_device *phydev)
2004 +{
2005 + int ret;
2006 +
2007 + ret = genphy_config_aneg(phydev);
2008 + if (ret < 0)
2009 + return ret;
2010 +
2011 + /* Quirk was copied from vendor driver. Unfortunately it includes no
2012 + * description of the magic numbers.
2013 + */
2014 + if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
2015 + phy_write(phydev, 0x17, 0x2138);
2016 + phy_write(phydev, 0x0e, 0x0260);
2017 + } else {
2018 + phy_write(phydev, 0x17, 0x2108);
2019 + phy_write(phydev, 0x0e, 0x0000);
2020 + }
2021 +
2022 + return 0;
2023 +}
2024 +
2025 +static int rtl8211c_config_init(struct phy_device *phydev)
2026 +{
2027 + /* RTL8211C has an issue when operating in Gigabit slave mode */
2028 + return phy_set_bits(phydev, MII_CTRL1000,
2029 + CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
2030 +}
2031 +
2032 +static int rtl8211f_config_init(struct phy_device *phydev)
2033 +{
2034 + struct rtl821x_priv *priv = phydev->priv;
2035 + struct device *dev = &phydev->mdio.dev;
2036 + u16 val_txdly, val_rxdly;
2037 + int ret;
2038 +
2039 + ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
2040 + RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
2041 + priv->phycr1);
2042 + if (ret < 0) {
2043 + dev_err(dev, "aldps mode configuration failed: %pe\n",
2044 + ERR_PTR(ret));
2045 + return ret;
2046 + }
2047 +
2048 + switch (phydev->interface) {
2049 + case PHY_INTERFACE_MODE_RGMII:
2050 + val_txdly = 0;
2051 + val_rxdly = 0;
2052 + break;
2053 +
2054 + case PHY_INTERFACE_MODE_RGMII_RXID:
2055 + val_txdly = 0;
2056 + val_rxdly = RTL8211F_RX_DELAY;
2057 + break;
2058 +
2059 + case PHY_INTERFACE_MODE_RGMII_TXID:
2060 + val_txdly = RTL8211F_TX_DELAY;
2061 + val_rxdly = 0;
2062 + break;
2063 +
2064 + case PHY_INTERFACE_MODE_RGMII_ID:
2065 + val_txdly = RTL8211F_TX_DELAY;
2066 + val_rxdly = RTL8211F_RX_DELAY;
2067 + break;
2068 +
2069 + default: /* the rest of the modes imply leaving delay as is. */
2070 + return 0;
2071 + }
2072 +
2073 + ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
2074 + val_txdly);
2075 + if (ret < 0) {
2076 + dev_err(dev, "Failed to update the TX delay register\n");
2077 + return ret;
2078 + } else if (ret) {
2079 + dev_dbg(dev,
2080 + "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
2081 + val_txdly ? "Enabling" : "Disabling");
2082 + } else {
2083 + dev_dbg(dev,
2084 + "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
2085 + val_txdly ? "enabled" : "disabled");
2086 + }
2087 +
2088 + ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
2089 + val_rxdly);
2090 + if (ret < 0) {
2091 + dev_err(dev, "Failed to update the RX delay register\n");
2092 + return ret;
2093 + } else if (ret) {
2094 + dev_dbg(dev,
2095 + "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
2096 + val_rxdly ? "Enabling" : "Disabling");
2097 + } else {
2098 + dev_dbg(dev,
2099 + "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
2100 + val_rxdly ? "enabled" : "disabled");
2101 + }
2102 +
2103 + if (priv->has_phycr2) {
2104 + ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
2105 + RTL8211F_CLKOUT_EN, priv->phycr2);
2106 + if (ret < 0) {
2107 + dev_err(dev, "clkout configuration failed: %pe\n",
2108 + ERR_PTR(ret));
2109 + return ret;
2110 + }
2111 +
2112 + return genphy_soft_reset(phydev);
2113 + }
2114 +
2115 + return 0;
2116 +}
2117 +
2118 +static int rtl821x_suspend(struct phy_device *phydev)
2119 +{
2120 + struct rtl821x_priv *priv = phydev->priv;
2121 + int ret = 0;
2122 +
2123 + if (!phydev->wol_enabled) {
2124 + ret = genphy_suspend(phydev);
2125 +
2126 + if (ret)
2127 + return ret;
2128 +
2129 + clk_disable_unprepare(priv->clk);
2130 + }
2131 +
2132 + return ret;
2133 +}
2134 +
2135 +static int rtl821x_resume(struct phy_device *phydev)
2136 +{
2137 + struct rtl821x_priv *priv = phydev->priv;
2138 + int ret;
2139 +
2140 + if (!phydev->wol_enabled)
2141 + clk_prepare_enable(priv->clk);
2142 +
2143 + ret = genphy_resume(phydev);
2144 + if (ret < 0)
2145 + return ret;
2146 +
2147 + msleep(20);
2148 +
2149 + return 0;
2150 +}
2151 +
2152 +static int rtl8211f_led_hw_is_supported(struct phy_device *phydev, u8 index,
2153 + unsigned long rules)
2154 +{
2155 + const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) |
2156 + BIT(TRIGGER_NETDEV_LINK_100) |
2157 + BIT(TRIGGER_NETDEV_LINK_1000) |
2158 + BIT(TRIGGER_NETDEV_RX) |
2159 + BIT(TRIGGER_NETDEV_TX);
2160 +
2161 + /* The RTL8211F PHY supports these LED settings on up to three LEDs:
2162 + * - Link: Configurable subset of 10/100/1000 link rates
2163 + * - Active: Blink on activity, RX or TX is not differentiated
2164 + * The Active option has two modes, A and B:
2165 + * - A: Link and Active indication at configurable, but matching,
2166 + * subset of 10/100/1000 link rates
2167 + * - B: Link indication at configurable subset of 10/100/1000 link
2168 + * rates and Active indication always at all three 10+100+1000
2169 + * link rates.
2170 + * This code currently uses mode B only.
2171 + */
2172 +
2173 + if (index >= RTL8211F_LED_COUNT)
2174 + return -EINVAL;
2175 +
2176 + /* Filter out any other unsupported triggers. */
2177 + if (rules & ~mask)
2178 + return -EOPNOTSUPP;
2179 +
2180 + /* RX and TX are not differentiated, either both are set or not set. */
2181 + if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX)))
2182 + return -EOPNOTSUPP;
2183 +
2184 + return 0;
2185 +}
2186 +
2187 +static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index,
2188 + unsigned long *rules)
2189 +{
2190 + int val;
2191 +
2192 + if (index >= RTL8211F_LED_COUNT)
2193 + return -EINVAL;
2194 +
2195 + val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR);
2196 + if (val < 0)
2197 + return val;
2198 +
2199 + val >>= RTL8211F_LEDCR_SHIFT * index;
2200 + val &= RTL8211F_LEDCR_MASK;
2201 +
2202 + if (val & RTL8211F_LEDCR_LINK_10)
2203 + set_bit(TRIGGER_NETDEV_LINK_10, rules);
2204 +
2205 + if (val & RTL8211F_LEDCR_LINK_100)
2206 + set_bit(TRIGGER_NETDEV_LINK_100, rules);
2207 +
2208 + if (val & RTL8211F_LEDCR_LINK_1000)
2209 + set_bit(TRIGGER_NETDEV_LINK_1000, rules);
2210 +
2211 + if (val & RTL8211F_LEDCR_ACT_TXRX) {
2212 + set_bit(TRIGGER_NETDEV_RX, rules);
2213 + set_bit(TRIGGER_NETDEV_TX, rules);
2214 + }
2215 +
2216 + return 0;
2217 +}
2218 +
2219 +static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index,
2220 + unsigned long rules)
2221 +{
2222 + const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index);
2223 + u16 reg = 0;
2224 +
2225 + if (index >= RTL8211F_LED_COUNT)
2226 + return -EINVAL;
2227 +
2228 + if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
2229 + reg |= RTL8211F_LEDCR_LINK_10;
2230 +
2231 + if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
2232 + reg |= RTL8211F_LEDCR_LINK_100;
2233 +
2234 + if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
2235 + reg |= RTL8211F_LEDCR_LINK_1000;
2236 +
2237 + if (test_bit(TRIGGER_NETDEV_RX, &rules) ||
2238 + test_bit(TRIGGER_NETDEV_TX, &rules)) {
2239 + reg |= RTL8211F_LEDCR_ACT_TXRX;
2240 + }
2241 +
2242 + reg <<= RTL8211F_LEDCR_SHIFT * index;
2243 + reg |= RTL8211F_LEDCR_MODE; /* Mode B */
2244 +
2245 + return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg);
2246 +}
2247 +
2248 +static int rtl8211e_config_init(struct phy_device *phydev)
2249 +{
2250 + int ret = 0, oldpage;
2251 + u16 val;
2252 +
2253 + /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
2254 + switch (phydev->interface) {
2255 + case PHY_INTERFACE_MODE_RGMII:
2256 + val = RTL8211E_CTRL_DELAY | 0;
2257 + break;
2258 + case PHY_INTERFACE_MODE_RGMII_ID:
2259 + val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
2260 + break;
2261 + case PHY_INTERFACE_MODE_RGMII_RXID:
2262 + val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
2263 + break;
2264 + case PHY_INTERFACE_MODE_RGMII_TXID:
2265 + val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
2266 + break;
2267 + default: /* the rest of the modes imply leaving delays as is. */
2268 + return 0;
2269 + }
2270 +
2271 + /* According to a sample driver there is a 0x1c config register on the
2272 + * 0xa4 extension page (0x7) layout. It can be used to disable/enable
2273 + * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
2274 + * The configuration register definition:
2275 + * 14 = reserved
2276 + * 13 = Force Tx RX Delay controlled by bit12 bit11,
2277 + * 12 = RX Delay, 11 = TX Delay
2278 + * 10:0 = Test && debug settings reserved by realtek
2279 + */
2280 + oldpage = phy_select_page(phydev, 0x7);
2281 + if (oldpage < 0)
2282 + goto err_restore_page;
2283 +
2284 + ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
2285 + if (ret)
2286 + goto err_restore_page;
2287 +
2288 + ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
2289 + | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
2290 + val);
2291 +
2292 +err_restore_page:
2293 + return phy_restore_page(phydev, oldpage, ret);
2294 +}
2295 +
2296 +static int rtl8211b_suspend(struct phy_device *phydev)
2297 +{
2298 + phy_write(phydev, MII_MMD_DATA, BIT(9));
2299 +
2300 + return genphy_suspend(phydev);
2301 +}
2302 +
2303 +static int rtl8211b_resume(struct phy_device *phydev)
2304 +{
2305 + phy_write(phydev, MII_MMD_DATA, 0);
2306 +
2307 + return genphy_resume(phydev);
2308 +}
2309 +
2310 +static int rtl8366rb_config_init(struct phy_device *phydev)
2311 +{
2312 + int ret;
2313 +
2314 + ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
2315 + RTL8366RB_POWER_SAVE_ON);
2316 + if (ret) {
2317 + dev_err(&phydev->mdio.dev,
2318 + "error enabling power management\n");
2319 + }
2320 +
2321 + return ret;
2322 +}
2323 +
2324 +/* get actual speed to cover the downshift case */
2325 +static void rtlgen_decode_physr(struct phy_device *phydev, int val)
2326 +{
2327 + /* bit 3
2328 + * 0: Half Duplex
2329 + * 1: Full Duplex
2330 + */
2331 + if (val & RTL_VND2_PHYSR_DUPLEX)
2332 + phydev->duplex = DUPLEX_FULL;
2333 + else
2334 + phydev->duplex = DUPLEX_HALF;
2335 +
2336 + switch (val & RTL_VND2_PHYSR_SPEED_MASK) {
2337 + case 0x0000:
2338 + phydev->speed = SPEED_10;
2339 + break;
2340 + case 0x0010:
2341 + phydev->speed = SPEED_100;
2342 + break;
2343 + case 0x0020:
2344 + phydev->speed = SPEED_1000;
2345 + break;
2346 + case 0x0200:
2347 + phydev->speed = SPEED_10000;
2348 + break;
2349 + case 0x0210:
2350 + phydev->speed = SPEED_2500;
2351 + break;
2352 + case 0x0220:
2353 + phydev->speed = SPEED_5000;
2354 + break;
2355 + default:
2356 + break;
2357 + }
2358 +
2359 + /* bit 11
2360 + * 0: Slave Mode
2361 + * 1: Master Mode
2362 + */
2363 + if (phydev->speed >= 1000) {
2364 + if (val & RTL_VND2_PHYSR_MASTER)
2365 + phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
2366 + else
2367 + phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
2368 + } else {
2369 + phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
2370 + }
2371 +}
2372 +
2373 +static int rtlgen_read_status(struct phy_device *phydev)
2374 +{
2375 + int ret, val;
2376 +
2377 + ret = genphy_read_status(phydev);
2378 + if (ret < 0)
2379 + return ret;
2380 +
2381 + if (!phydev->link)
2382 + return 0;
2383 +
2384 + val = phy_read_paged(phydev, 0xa43, 0x12);
2385 + if (val < 0)
2386 + return val;
2387 +
2388 + rtlgen_decode_physr(phydev, val);
2389 +
2390 + return 0;
2391 +}
2392 +
2393 +static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
2394 +{
2395 + int ret;
2396 +
2397 + if (devnum == MDIO_MMD_VEND2) {
2398 + rtl821x_write_page(phydev, regnum >> 4);
2399 + ret = __phy_read(phydev, 0x10 + ((regnum & 0xf) >> 1));
2400 + rtl821x_write_page(phydev, 0);
2401 + } else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
2402 + rtl821x_write_page(phydev, 0xa5c);
2403 + ret = __phy_read(phydev, 0x12);
2404 + rtl821x_write_page(phydev, 0);
2405 + } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
2406 + rtl821x_write_page(phydev, 0xa5d);
2407 + ret = __phy_read(phydev, 0x10);
2408 + rtl821x_write_page(phydev, 0);
2409 + } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
2410 + rtl821x_write_page(phydev, 0xa5d);
2411 + ret = __phy_read(phydev, 0x11);
2412 + rtl821x_write_page(phydev, 0);
2413 + } else {
2414 + ret = -EOPNOTSUPP;
2415 + }
2416 +
2417 + return ret;
2418 +}
2419 +
2420 +static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
2421 + u16 val)
2422 +{
2423 + int ret;
2424 +
2425 + if (devnum == MDIO_MMD_VEND2) {
2426 + rtl821x_write_page(phydev, regnum >> 4);
2427 + ret = __phy_write(phydev, 0x10 + ((regnum & 0xf) >> 1), val);
2428 + rtl821x_write_page(phydev, 0);
2429 + } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
2430 + rtl821x_write_page(phydev, 0xa5d);
2431 + ret = __phy_write(phydev, 0x10, val);
2432 + rtl821x_write_page(phydev, 0);
2433 + } else {
2434 + ret = -EOPNOTSUPP;
2435 + }
2436 +
2437 + return ret;
2438 +}
2439 +
2440 +static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
2441 +{
2442 + int ret = rtlgen_read_mmd(phydev, devnum, regnum);
2443 +
2444 + if (ret != -EOPNOTSUPP)
2445 + return ret;
2446 +
2447 + if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
2448 + rtl821x_write_page(phydev, 0xa6e);
2449 + ret = __phy_read(phydev, 0x16);
2450 + rtl821x_write_page(phydev, 0);
2451 + } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
2452 + rtl821x_write_page(phydev, 0xa6d);
2453 + ret = __phy_read(phydev, 0x12);
2454 + rtl821x_write_page(phydev, 0);
2455 + } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
2456 + rtl821x_write_page(phydev, 0xa6d);
2457 + ret = __phy_read(phydev, 0x10);
2458 + rtl821x_write_page(phydev, 0);
2459 + }
2460 +
2461 + return ret;
2462 +}
2463 +
2464 +static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
2465 + u16 val)
2466 +{
2467 + int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
2468 +
2469 + if (ret != -EOPNOTSUPP)
2470 + return ret;
2471 +
2472 + if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
2473 + rtl821x_write_page(phydev, 0xa6d);
2474 + ret = __phy_write(phydev, 0x12, val);
2475 + rtl821x_write_page(phydev, 0);
2476 + }
2477 +
2478 + return ret;
2479 +}
2480 +
2481 +static int rtl822xb_config_init(struct phy_device *phydev)
2482 +{
2483 + bool has_2500, has_sgmii;
2484 + u16 mode;
2485 + int ret;
2486 +
2487 + has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX,
2488 + phydev->host_interfaces) ||
2489 + phydev->interface == PHY_INTERFACE_MODE_2500BASEX;
2490 +
2491 + has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII,
2492 + phydev->host_interfaces) ||
2493 + phydev->interface == PHY_INTERFACE_MODE_SGMII;
2494 +
2495 + /* fill in possible interfaces */
2496 + __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces,
2497 + has_2500);
2498 + __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces,
2499 + has_sgmii);
2500 +
2501 + if (!has_2500 && !has_sgmii)
2502 + return 0;
2503 +
2504 + /* determine SerDes option mode */
2505 + if (has_2500 && !has_sgmii) {
2506 + mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX;
2507 + phydev->rate_matching = RATE_MATCH_PAUSE;
2508 + } else {
2509 + mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII;
2510 + phydev->rate_matching = RATE_MATCH_NONE;
2511 + }
2512 +
2513 + /* the following sequence with magic numbers sets up the SerDes
2514 + * option mode
2515 + */
2516 + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0);
2517 + if (ret < 0)
2518 + return ret;
2519 +
2520 + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1,
2521 + RTL822X_VND1_SERDES_OPTION,
2522 + RTL822X_VND1_SERDES_OPTION_MODE_MASK,
2523 + mode);
2524 + if (ret < 0)
2525 + return ret;
2526 +
2527 + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503);
2528 + if (ret < 0)
2529 + return ret;
2530 +
2531 + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455);
2532 + if (ret < 0)
2533 + return ret;
2534 +
2535 + return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020);
2536 +}
2537 +
2538 +static int rtl822xb_get_rate_matching(struct phy_device *phydev,
2539 + phy_interface_t iface)
2540 +{
2541 + int val;
2542 +
2543 + /* Only rate matching at 2500base-x */
2544 + if (iface != PHY_INTERFACE_MODE_2500BASEX)
2545 + return RATE_MATCH_NONE;
2546 +
2547 + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION);
2548 + if (val < 0)
2549 + return val;
2550 +
2551 + if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) ==
2552 + RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX)
2553 + return RATE_MATCH_PAUSE;
2554 +
2555 + /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */
2556 + return RATE_MATCH_NONE;
2557 +}
2558 +
2559 +static int rtl822x_get_features(struct phy_device *phydev)
2560 +{
2561 + int val;
2562 +
2563 + val = phy_read_paged(phydev, 0xa61, 0x13);
2564 + if (val < 0)
2565 + return val;
2566 +
2567 + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
2568 + phydev->supported, val & MDIO_PMA_SPEED_2_5G);
2569 + linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
2570 + phydev->supported, val & MDIO_PMA_SPEED_5G);
2571 + linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2572 + phydev->supported, val & MDIO_SPEED_10G);
2573 +
2574 + return genphy_read_abilities(phydev);
2575 +}
2576 +
2577 +static int rtl822x_config_aneg(struct phy_device *phydev)
2578 +{
2579 + int ret = 0;
2580 +
2581 + if (phydev->autoneg == AUTONEG_ENABLE) {
2582 + u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
2583 +
2584 + ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
2585 + MDIO_AN_10GBT_CTRL_ADV2_5G |
2586 + MDIO_AN_10GBT_CTRL_ADV5G,
2587 + adv);
2588 + if (ret < 0)
2589 + return ret;
2590 + }
2591 +
2592 + return __genphy_config_aneg(phydev, ret);
2593 +}
2594 +
2595 +static void rtl822xb_update_interface(struct phy_device *phydev)
2596 +{
2597 + int val;
2598 +
2599 + if (!phydev->link)
2600 + return;
2601 +
2602 + /* Change interface according to serdes mode */
2603 + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3);
2604 + if (val < 0)
2605 + return;
2606 +
2607 + switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) {
2608 + case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX:
2609 + phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
2610 + break;
2611 + case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII:
2612 + phydev->interface = PHY_INTERFACE_MODE_SGMII;
2613 + break;
2614 + }
2615 +}
2616 +
2617 +static int rtl822x_read_status(struct phy_device *phydev)
2618 +{
2619 + int lpadv, ret;
2620 +
2621 + mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
2622 +
2623 + ret = rtlgen_read_status(phydev);
2624 + if (ret < 0)
2625 + return ret;
2626 +
2627 + if (phydev->autoneg == AUTONEG_DISABLE ||
2628 + !phydev->autoneg_complete)
2629 + return 0;
2630 +
2631 + lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
2632 + if (lpadv < 0)
2633 + return lpadv;
2634 +
2635 + mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv);
2636 +
2637 + return 0;
2638 +}
2639 +
2640 +static int rtl822xb_read_status(struct phy_device *phydev)
2641 +{
2642 + int ret;
2643 +
2644 + ret = rtl822x_read_status(phydev);
2645 + if (ret < 0)
2646 + return ret;
2647 +
2648 + rtl822xb_update_interface(phydev);
2649 +
2650 + return 0;
2651 +}
2652 +
2653 +static int rtl822x_c45_get_features(struct phy_device *phydev)
2654 +{
2655 + linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
2656 + phydev->supported);
2657 +
2658 + return genphy_c45_pma_read_abilities(phydev);
2659 +}
2660 +
2661 +static int rtl822x_c45_config_aneg(struct phy_device *phydev)
2662 +{
2663 + bool changed = false;
2664 + int ret, val;
2665 +
2666 + if (phydev->autoneg == AUTONEG_DISABLE)
2667 + return genphy_c45_pma_setup_forced(phydev);
2668 +
2669 + ret = genphy_c45_an_config_aneg(phydev);
2670 + if (ret < 0)
2671 + return ret;
2672 + if (ret > 0)
2673 + changed = true;
2674 +
2675 + val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
2676 +
2677 + /* Vendor register as C45 has no standardized support for 1000BaseT */
2678 + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL822X_VND2_GBCR,
2679 + ADVERTISE_1000FULL, val);
2680 + if (ret < 0)
2681 + return ret;
2682 + if (ret > 0)
2683 + changed = true;
2684 +
2685 + return genphy_c45_check_and_restart_aneg(phydev, changed);
2686 +}
2687 +
2688 +static int rtl822x_c45_read_status(struct phy_device *phydev)
2689 +{
2690 + int ret, val;
2691 +
2692 + /* Vendor register as C45 has no standardized support for 1000BaseT */
2693 + if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) {
2694 + val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
2695 + RTL822X_VND2_GANLPAR);
2696 + if (val < 0)
2697 + return val;
2698 + } else {
2699 + val = 0;
2700 + }
2701 + mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
2702 +
2703 + ret = genphy_c45_read_status(phydev);
2704 + if (ret < 0)
2705 + return ret;
2706 +
2707 + if (!phydev->link) {
2708 + phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
2709 + return 0;
2710 + }
2711 +
2712 + /* Read actual speed from vendor register. */
2713 + val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR);
2714 + if (val < 0)
2715 + return val;
2716 +
2717 + rtlgen_decode_physr(phydev, val);
2718 +
2719 + return 0;
2720 +}
2721 +
2722 +static int rtl822xb_c45_read_status(struct phy_device *phydev)
2723 +{
2724 + int ret;
2725 +
2726 + ret = rtl822x_c45_read_status(phydev);
2727 + if (ret < 0)
2728 + return ret;
2729 +
2730 + rtl822xb_update_interface(phydev);
2731 +
2732 + return 0;
2733 +}
2734 +
2735 +static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
2736 +{
2737 + int val;
2738 +
2739 + phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
2740 + val = phy_read(phydev, 0x13);
2741 + phy_write(phydev, RTL821x_PAGE_SELECT, 0);
2742 +
2743 + return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
2744 +}
2745 +
2746 +/* On internal PHY's MMD reads over C22 always return 0.
2747 + * Check a MMD register which is known to be non-zero.
2748 + */
2749 +static bool rtlgen_supports_mmd(struct phy_device *phydev)
2750 +{
2751 + int val;
2752 +
2753 + phy_lock_mdio_bus(phydev);
2754 + __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS);
2755 + __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE);
2756 + __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR);
2757 + val = __phy_read(phydev, MII_MMD_DATA);
2758 + phy_unlock_mdio_bus(phydev);
2759 +
2760 + return val > 0;
2761 +}
2762 +
2763 +static int rtlgen_match_phy_device(struct phy_device *phydev)
2764 +{
2765 + return phydev->phy_id == RTL_GENERIC_PHYID &&
2766 + !rtlgen_supports_2_5gbps(phydev);
2767 +}
2768 +
2769 +static int rtl8226_match_phy_device(struct phy_device *phydev)
2770 +{
2771 + return phydev->phy_id == RTL_GENERIC_PHYID &&
2772 + rtlgen_supports_2_5gbps(phydev) &&
2773 + rtlgen_supports_mmd(phydev);
2774 +}
2775 +
2776 +static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
2777 + bool is_c45)
2778 +{
2779 + if (phydev->is_c45)
2780 + return is_c45 && (id == phydev->c45_ids.device_ids[1]);
2781 + else
2782 + return !is_c45 && (id == phydev->phy_id);
2783 +}
2784 +
2785 +static int rtl8221b_match_phy_device(struct phy_device *phydev)
2786 +{
2787 + return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev);
2788 +}
2789 +
2790 +static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev)
2791 +{
2792 + return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);
2793 +}
2794 +
2795 +static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev)
2796 +{
2797 + return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true);
2798 +}
2799 +
2800 +static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev)
2801 +{
2802 + return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false);
2803 +}
2804 +
2805 +static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev)
2806 +{
2807 + return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true);
2808 +}
2809 +
2810 +static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev)
2811 +{
2812 + if (phydev->is_c45)
2813 + return false;
2814 +
2815 + switch (phydev->phy_id) {
2816 + case RTL_GENERIC_PHYID:
2817 + case RTL_8221B:
2818 + case RTL_8251B:
2819 + case 0x001cc841:
2820 + break;
2821 + default:
2822 + return false;
2823 + }
2824 +
2825 + return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev);
2826 +}
2827 +
2828 +static int rtl8251b_c45_match_phy_device(struct phy_device *phydev)
2829 +{
2830 + return rtlgen_is_c45_match(phydev, RTL_8251B, true);
2831 +}
2832 +
2833 +static int rtlgen_resume(struct phy_device *phydev)
2834 +{
2835 + int ret = genphy_resume(phydev);
2836 +
2837 + /* Internal PHY's from RTL8168h up may not be instantly ready */
2838 + msleep(20);
2839 +
2840 + return ret;
2841 +}
2842 +
2843 +static int rtlgen_c45_resume(struct phy_device *phydev)
2844 +{
2845 + int ret = genphy_c45_pma_resume(phydev);
2846 +
2847 + msleep(20);
2848 +
2849 + return ret;
2850 +}
2851 +
2852 +static int rtl9000a_config_init(struct phy_device *phydev)
2853 +{
2854 + phydev->autoneg = AUTONEG_DISABLE;
2855 + phydev->speed = SPEED_100;
2856 + phydev->duplex = DUPLEX_FULL;
2857 +
2858 + return 0;
2859 +}
2860 +
2861 +static int rtl9000a_config_aneg(struct phy_device *phydev)
2862 +{
2863 + int ret;
2864 + u16 ctl = 0;
2865 +
2866 + switch (phydev->master_slave_set) {
2867 + case MASTER_SLAVE_CFG_MASTER_FORCE:
2868 + ctl |= CTL1000_AS_MASTER;
2869 + break;
2870 + case MASTER_SLAVE_CFG_SLAVE_FORCE:
2871 + break;
2872 + case MASTER_SLAVE_CFG_UNKNOWN:
2873 + case MASTER_SLAVE_CFG_UNSUPPORTED:
2874 + return 0;
2875 + default:
2876 + phydev_warn(phydev, "Unsupported Master/Slave mode\n");
2877 + return -EOPNOTSUPP;
2878 + }
2879 +
2880 + ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
2881 + if (ret == 1)
2882 + ret = genphy_soft_reset(phydev);
2883 +
2884 + return ret;
2885 +}
2886 +
2887 +static int rtl9000a_read_status(struct phy_device *phydev)
2888 +{
2889 + int ret;
2890 +
2891 + phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
2892 + phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
2893 +
2894 + ret = genphy_update_link(phydev);
2895 + if (ret)
2896 + return ret;
2897 +
2898 + ret = phy_read(phydev, MII_CTRL1000);
2899 + if (ret < 0)
2900 + return ret;
2901 + if (ret & CTL1000_AS_MASTER)
2902 + phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
2903 + else
2904 + phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
2905 +
2906 + ret = phy_read(phydev, MII_STAT1000);
2907 + if (ret < 0)
2908 + return ret;
2909 + if (ret & LPA_1000MSRES)
2910 + phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
2911 + else
2912 + phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
2913 +
2914 + return 0;
2915 +}
2916 +
2917 +static int rtl9000a_ack_interrupt(struct phy_device *phydev)
2918 +{
2919 + int err;
2920 +
2921 + err = phy_read(phydev, RTL8211F_INSR);
2922 +
2923 + return (err < 0) ? err : 0;
2924 +}
2925 +
2926 +static int rtl9000a_config_intr(struct phy_device *phydev)
2927 +{
2928 + u16 val;
2929 + int err;
2930 +
2931 + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
2932 + err = rtl9000a_ack_interrupt(phydev);
2933 + if (err)
2934 + return err;
2935 +
2936 + val = (u16)~RTL9000A_GINMR_LINK_STATUS;
2937 + err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
2938 + } else {
2939 + val = ~0;
2940 + err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
2941 + if (err)
2942 + return err;
2943 +
2944 + err = rtl9000a_ack_interrupt(phydev);
2945 + }
2946 +
2947 + return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
2948 +}
2949 +
2950 +static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
2951 +{
2952 + int irq_status;
2953 +
2954 + irq_status = phy_read(phydev, RTL8211F_INSR);
2955 + if (irq_status < 0) {
2956 + phy_error(phydev);
2957 + return IRQ_NONE;
2958 + }
2959 +
2960 + if (!(irq_status & RTL8211F_INER_LINK_STATUS))
2961 + return IRQ_NONE;
2962 +
2963 + phy_trigger_machine(phydev);
2964 +
2965 + return IRQ_HANDLED;
2966 +}
2967 +
2968 +static struct phy_driver realtek_drvs[] = {
2969 + {
2970 + PHY_ID_MATCH_EXACT(0x00008201),
2971 + .name = "RTL8201CP Ethernet",
2972 + .read_page = rtl821x_read_page,
2973 + .write_page = rtl821x_write_page,
2974 + }, {
2975 + PHY_ID_MATCH_EXACT(0x001cc816),
2976 + .name = "RTL8201F Fast Ethernet",
2977 + .config_intr = &rtl8201_config_intr,
2978 + .handle_interrupt = rtl8201_handle_interrupt,
2979 + .suspend = genphy_suspend,
2980 + .resume = genphy_resume,
2981 + .read_page = rtl821x_read_page,
2982 + .write_page = rtl821x_write_page,
2983 + }, {
2984 + PHY_ID_MATCH_MODEL(0x001cc880),
2985 + .name = "RTL8208 Fast Ethernet",
2986 + .read_mmd = genphy_read_mmd_unsupported,
2987 + .write_mmd = genphy_write_mmd_unsupported,
2988 + .suspend = genphy_suspend,
2989 + .resume = genphy_resume,
2990 + .read_page = rtl821x_read_page,
2991 + .write_page = rtl821x_write_page,
2992 + }, {
2993 + PHY_ID_MATCH_EXACT(0x001cc910),
2994 + .name = "RTL8211 Gigabit Ethernet",
2995 + .config_aneg = rtl8211_config_aneg,
2996 + .read_mmd = &genphy_read_mmd_unsupported,
2997 + .write_mmd = &genphy_write_mmd_unsupported,
2998 + .read_page = rtl821x_read_page,
2999 + .write_page = rtl821x_write_page,
3000 + }, {
3001 + PHY_ID_MATCH_EXACT(0x001cc912),
3002 + .name = "RTL8211B Gigabit Ethernet",
3003 + .config_intr = &rtl8211b_config_intr,
3004 + .handle_interrupt = rtl821x_handle_interrupt,
3005 + .read_mmd = &genphy_read_mmd_unsupported,
3006 + .write_mmd = &genphy_write_mmd_unsupported,
3007 + .suspend = rtl8211b_suspend,
3008 + .resume = rtl8211b_resume,
3009 + .read_page = rtl821x_read_page,
3010 + .write_page = rtl821x_write_page,
3011 + }, {
3012 + PHY_ID_MATCH_EXACT(0x001cc913),
3013 + .name = "RTL8211C Gigabit Ethernet",
3014 + .config_init = rtl8211c_config_init,
3015 + .read_mmd = &genphy_read_mmd_unsupported,
3016 + .write_mmd = &genphy_write_mmd_unsupported,
3017 + .read_page = rtl821x_read_page,
3018 + .write_page = rtl821x_write_page,
3019 + }, {
3020 + PHY_ID_MATCH_EXACT(0x001cc914),
3021 + .name = "RTL8211DN Gigabit Ethernet",
3022 + .config_intr = rtl8211e_config_intr,
3023 + .handle_interrupt = rtl821x_handle_interrupt,
3024 + .suspend = genphy_suspend,
3025 + .resume = genphy_resume,
3026 + .read_page = rtl821x_read_page,
3027 + .write_page = rtl821x_write_page,
3028 + }, {
3029 + PHY_ID_MATCH_EXACT(0x001cc915),
3030 + .name = "RTL8211E Gigabit Ethernet",
3031 + .config_init = &rtl8211e_config_init,
3032 + .config_intr = &rtl8211e_config_intr,
3033 + .handle_interrupt = rtl821x_handle_interrupt,
3034 + .suspend = genphy_suspend,
3035 + .resume = genphy_resume,
3036 + .read_page = rtl821x_read_page,
3037 + .write_page = rtl821x_write_page,
3038 + }, {
3039 + PHY_ID_MATCH_EXACT(0x001cc916),
3040 + .name = "RTL8211F Gigabit Ethernet",
3041 + .probe = rtl821x_probe,
3042 + .config_init = &rtl8211f_config_init,
3043 + .read_status = rtlgen_read_status,
3044 + .config_intr = &rtl8211f_config_intr,
3045 + .handle_interrupt = rtl8211f_handle_interrupt,
3046 + .suspend = rtl821x_suspend,
3047 + .resume = rtl821x_resume,
3048 + .read_page = rtl821x_read_page,
3049 + .write_page = rtl821x_write_page,
3050 + .flags = PHY_ALWAYS_CALL_SUSPEND,
3051 + .led_hw_is_supported = rtl8211f_led_hw_is_supported,
3052 + .led_hw_control_get = rtl8211f_led_hw_control_get,
3053 + .led_hw_control_set = rtl8211f_led_hw_control_set,
3054 + }, {
3055 + PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID),
3056 + .name = "RTL8211F-VD Gigabit Ethernet",
3057 + .probe = rtl821x_probe,
3058 + .config_init = &rtl8211f_config_init,
3059 + .read_status = rtlgen_read_status,
3060 + .config_intr = &rtl8211f_config_intr,
3061 + .handle_interrupt = rtl8211f_handle_interrupt,
3062 + .suspend = rtl821x_suspend,
3063 + .resume = rtl821x_resume,
3064 + .read_page = rtl821x_read_page,
3065 + .write_page = rtl821x_write_page,
3066 + .flags = PHY_ALWAYS_CALL_SUSPEND,
3067 + }, {
3068 + .name = "Generic FE-GE Realtek PHY",
3069 + .match_phy_device = rtlgen_match_phy_device,
3070 + .read_status = rtlgen_read_status,
3071 + .suspend = genphy_suspend,
3072 + .resume = rtlgen_resume,
3073 + .read_page = rtl821x_read_page,
3074 + .write_page = rtl821x_write_page,
3075 + .read_mmd = rtlgen_read_mmd,
3076 + .write_mmd = rtlgen_write_mmd,
3077 + }, {
3078 + .name = "RTL8226 2.5Gbps PHY",
3079 + .match_phy_device = rtl8226_match_phy_device,
3080 + .get_features = rtl822x_get_features,
3081 + .config_aneg = rtl822x_config_aneg,
3082 + .read_status = rtl822x_read_status,
3083 + .suspend = genphy_suspend,
3084 + .resume = rtlgen_resume,
3085 + .read_page = rtl821x_read_page,
3086 + .write_page = rtl821x_write_page,
3087 + }, {
3088 + .match_phy_device = rtl8221b_match_phy_device,
3089 + .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
3090 + .get_features = rtl822x_get_features,
3091 + .config_aneg = rtl822x_config_aneg,
3092 + .config_init = rtl822xb_config_init,
3093 + .get_rate_matching = rtl822xb_get_rate_matching,
3094 + .read_status = rtl822xb_read_status,
3095 + .suspend = genphy_suspend,
3096 + .resume = rtlgen_resume,
3097 + .read_page = rtl821x_read_page,
3098 + .write_page = rtl821x_write_page,
3099 + }, {
3100 + PHY_ID_MATCH_EXACT(0x001cc838),
3101 + .name = "RTL8226-CG 2.5Gbps PHY",
3102 + .get_features = rtl822x_get_features,
3103 + .config_aneg = rtl822x_config_aneg,
3104 + .read_status = rtl822x_read_status,
3105 + .suspend = genphy_suspend,
3106 + .resume = rtlgen_resume,
3107 + .read_page = rtl821x_read_page,
3108 + .write_page = rtl821x_write_page,
3109 + }, {
3110 + PHY_ID_MATCH_EXACT(0x001cc848),
3111 + .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
3112 + .get_features = rtl822x_get_features,
3113 + .config_aneg = rtl822x_config_aneg,
3114 + .config_init = rtl822xb_config_init,
3115 + .get_rate_matching = rtl822xb_get_rate_matching,
3116 + .read_status = rtl822xb_read_status,
3117 + .suspend = genphy_suspend,
3118 + .resume = rtlgen_resume,
3119 + .read_page = rtl821x_read_page,
3120 + .write_page = rtl821x_write_page,
3121 + }, {
3122 + .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
3123 + .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
3124 + .get_features = rtl822x_get_features,
3125 + .config_aneg = rtl822x_config_aneg,
3126 + .config_init = rtl822xb_config_init,
3127 + .get_rate_matching = rtl822xb_get_rate_matching,
3128 + .read_status = rtl822xb_read_status,
3129 + .suspend = genphy_suspend,
3130 + .resume = rtlgen_resume,
3131 + .read_page = rtl821x_read_page,
3132 + .write_page = rtl821x_write_page,
3133 + }, {
3134 + .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
3135 + .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
3136 + .config_init = rtl822xb_config_init,
3137 + .get_rate_matching = rtl822xb_get_rate_matching,
3138 + .get_features = rtl822x_c45_get_features,
3139 + .config_aneg = rtl822x_c45_config_aneg,
3140 + .read_status = rtl822xb_c45_read_status,
3141 + .suspend = genphy_c45_pma_suspend,
3142 + .resume = rtlgen_c45_resume,
3143 + }, {
3144 + .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device,
3145 + .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
3146 + .get_features = rtl822x_get_features,
3147 + .config_aneg = rtl822x_config_aneg,
3148 + .config_init = rtl822xb_config_init,
3149 + .get_rate_matching = rtl822xb_get_rate_matching,
3150 + .read_status = rtl822xb_read_status,
3151 + .suspend = genphy_suspend,
3152 + .resume = rtlgen_resume,
3153 + .read_page = rtl821x_read_page,
3154 + .write_page = rtl821x_write_page,
3155 + }, {
3156 + .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device,
3157 + .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",
3158 + .config_init = rtl822xb_config_init,
3159 + .get_rate_matching = rtl822xb_get_rate_matching,
3160 + .get_features = rtl822x_c45_get_features,
3161 + .config_aneg = rtl822x_c45_config_aneg,
3162 + .read_status = rtl822xb_c45_read_status,
3163 + .suspend = genphy_c45_pma_suspend,
3164 + .resume = rtlgen_c45_resume,
3165 + }, {
3166 + .match_phy_device = rtl8251b_c45_match_phy_device,
3167 + .name = "RTL8251B 5Gbps PHY",
3168 + .get_features = rtl822x_get_features,
3169 + .config_aneg = rtl822x_config_aneg,
3170 + .read_status = rtl822x_read_status,
3171 + .suspend = genphy_suspend,
3172 + .resume = rtlgen_resume,
3173 + .read_page = rtl821x_read_page,
3174 + .write_page = rtl821x_write_page,
3175 + }, {
3176 + .match_phy_device = rtl_internal_nbaset_match_phy_device,
3177 + .name = "Realtek Internal NBASE-T PHY",
3178 + .flags = PHY_IS_INTERNAL,
3179 + .get_features = rtl822x_get_features,
3180 + .config_aneg = rtl822x_config_aneg,
3181 + .read_status = rtl822x_read_status,
3182 + .suspend = genphy_suspend,
3183 + .resume = rtlgen_resume,
3184 + .read_page = rtl821x_read_page,
3185 + .write_page = rtl821x_write_page,
3186 + .read_mmd = rtl822x_read_mmd,
3187 + .write_mmd = rtl822x_write_mmd,
3188 + }, {
3189 + PHY_ID_MATCH_EXACT(0x001ccad0),
3190 + .name = "RTL8224 2.5Gbps PHY",
3191 + .get_features = rtl822x_c45_get_features,
3192 + .config_aneg = rtl822x_c45_config_aneg,
3193 + .read_status = rtl822x_c45_read_status,
3194 + .suspend = genphy_c45_pma_suspend,
3195 + .resume = rtlgen_c45_resume,
3196 + }, {
3197 + PHY_ID_MATCH_EXACT(0x001cc961),
3198 + .name = "RTL8366RB Gigabit Ethernet",
3199 + .config_init = &rtl8366rb_config_init,
3200 + /* These interrupts are handled by the irq controller
3201 + * embedded inside the RTL8366RB, they get unmasked when the
3202 + * irq is requested and ACKed by reading the status register,
3203 + * which is done by the irqchip code.
3204 + */
3205 + .config_intr = genphy_no_config_intr,
3206 + .handle_interrupt = genphy_handle_interrupt_no_ack,
3207 + .suspend = genphy_suspend,
3208 + .resume = genphy_resume,
3209 + }, {
3210 + PHY_ID_MATCH_EXACT(0x001ccb00),
3211 + .name = "RTL9000AA_RTL9000AN Ethernet",
3212 + .features = PHY_BASIC_T1_FEATURES,
3213 + .config_init = rtl9000a_config_init,
3214 + .config_aneg = rtl9000a_config_aneg,
3215 + .read_status = rtl9000a_read_status,
3216 + .config_intr = rtl9000a_config_intr,
3217 + .handle_interrupt = rtl9000a_handle_interrupt,
3218 + .suspend = genphy_suspend,
3219 + .resume = genphy_resume,
3220 + .read_page = rtl821x_read_page,
3221 + .write_page = rtl821x_write_page,
3222 + }, {
3223 + PHY_ID_MATCH_EXACT(0x001cc942),
3224 + .name = "RTL8365MB-VC Gigabit Ethernet",
3225 + /* Interrupt handling analogous to RTL8366RB */
3226 + .config_intr = genphy_no_config_intr,
3227 + .handle_interrupt = genphy_handle_interrupt_no_ack,
3228 + .suspend = genphy_suspend,
3229 + .resume = genphy_resume,
3230 + }, {
3231 + PHY_ID_MATCH_EXACT(0x001cc960),
3232 + .name = "RTL8366S Gigabit Ethernet",
3233 + .suspend = genphy_suspend,
3234 + .resume = genphy_resume,
3235 + .read_mmd = genphy_read_mmd_unsupported,
3236 + .write_mmd = genphy_write_mmd_unsupported,
3237 + },
3238 +};
3239 +
3240 +module_phy_driver(realtek_drvs);
3241 +
3242 +static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
3243 + { PHY_ID_MATCH_VENDOR(0x001cc800) },
3244 + { }
3245 +};
3246 +
3247 +MODULE_DEVICE_TABLE(mdio, realtek_tbl);
Mirror of https://github.com/openwrt/openwrt.git