1 From 8b9c12757f919157752646faf3821abf2b7d2a64 Mon Sep 17 00:00:00 2001
2 From: Chukun Pan <amadeus@jmu.edu.cn>
3 Date: Fri, 22 Nov 2024 15:30:05 +0800
4 Subject: [PATCH] arm64: dts: rockchip: add reset-names for combphy on rk3568
6 The reset-names of combphy are missing, add it.
8 Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
9 Fixes: fd3ac6e80497 ("dt-bindings: phy: rockchip: rk3588 has two reset lines")
10 Link: https://lore.kernel.org/r/20241122073006.99309-1-amadeus@jmu.edu.cn
11 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
13 arch/arm64/boot/dts/rockchip/rk3568.dtsi | 1 +
14 arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 ++
15 2 files changed, 3 insertions(+)
17 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
18 +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
20 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
21 assigned-clock-rates = <100000000>;
22 resets = <&cru SRST_PIPEPHY0>;
23 + reset-names = "phy";
24 rockchip,pipe-grf = <&pipegrf>;
25 rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
27 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
28 +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
30 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
31 assigned-clock-rates = <100000000>;
32 resets = <&cru SRST_PIPEPHY1>;
33 + reset-names = "phy";
34 rockchip,pipe-grf = <&pipegrf>;
35 rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
38 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
39 assigned-clock-rates = <100000000>;
40 resets = <&cru SRST_PIPEPHY2>;
41 + reset-names = "phy";
42 rockchip,pipe-grf = <&pipegrf>;
43 rockchip,pipe-phy-grf = <&pipe_phy_grf2>;