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   1 From patchwork Fri Nov  1 03:19:39 2024
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   5 X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
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   8  <linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
   9 Date: Fri, 1 Nov 2024 03:19:39 +0000
  10 From: Daniel Golle <daniel@makrotopia.org>
  11 To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org,
  12  linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Uwe
  13         =?iso-8859-1?q?Kleine-K=F6nig?= <u.kleine-koenig@baylibre.com>,
  14  Sam Shih <sam.shih@mediatek.com>, Frank Wunderlich <frank-w@public-files.de>,
  15  Daniel Golle <daniel@makrotopia.org>,
  16  AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
  17  Matthias Brugger <matthias.bgg@gmail.com>, Stephen Boyd <sboyd@kernel.org>,
  18  Michael Turquette <mturquette@baylibre.com>
  19 Subject: [PATCH] clk: mediatek: mt7988-infracfg: SPI0 clocks are not critical
  20 Message-ID: <ZyRIy22aS_Yjoavg@pidgin.makrotopia.org>
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  36  linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org
  37
  38 SPI0 clocks have wrongly been marked as critical while, probably due
  39 to the SPI driver not requesting them. This can (and should) be addressed
  40 in device tree instead.
  41 Remove CLK_IS_CRITICAL flag from clocks related to SPI0.
  42
  43 Fixes: 4b4719437d85 ("clk: mediatek: add drivers for MT7988 SoC")
  44 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  45 ---
  46  drivers/clk/mediatek/clk-mt7988-infracfg.c | 6 ++----
  47  1 file changed, 2 insertions(+), 4 deletions(-)
  48
  49 --- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
  50 +++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
  51 @@ -196,12 +196,10 @@ static const struct mtk_gate infra_clks[
  52         GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
  53         GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11,
  54                           CLK_IS_CRITICAL),
  55 -       GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12,
  56 -                         CLK_IS_CRITICAL),
  57 +       GATE_INFRA2(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12),
  58         GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13),
  59         GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14),
  60 -       GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15,
  61 -                         CLK_IS_CRITICAL),
  62 +       GATE_INFRA2(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15),
  63         GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16),
  64         GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17),
  65         GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18),