git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From faca6640521ef0c2fe422533993dd33895f4f7f2 Mon Sep 17 00:00:00 2001
   2 From: Dom Cobley <popcornmix@gmail.com>
   3 Date: Wed, 28 Jun 2023 16:24:29 +0100
   4 Subject: [PATCH 0568/1085] irqchip/irq-brcmstb-l2: Add config for 2711
   5  controller
   6
   7 We currently see these regularly:
   8 [   25.157560] irq 31, desc: 00000000c15e6d2c, depth: 0, count: 0, unhandled: 0
   9 [   25.164658] ->handle_irq():  00000000b1775675, brcmstb_l2_intc_irq_handle+0x0/0x1a8
  10 [   25.172352] ->irq_data.chip(): 00000000fea59f1c, gic_chip_mode1+0x0/0x108
  11 [   25.179166] ->action(): 000000003eda6d6f
  12 [   25.183096] ->action->handler(): 000000002c09e646, bad_chained_irq+0x0/0x58
  13 [   25.190084]      IRQ_LEVEL set
  14 [   25.193142]    IRQ_NOPROBE set
  15 [   25.196198]  IRQ_NOREQUEST set
  16 [   25.199255]   IRQ_NOTHREAD set
  17
  18 with:
  19 $ cat /proc/interrupts  | grep 31:
  20  31:          1          0          0          0     GICv2 129 Level     (null)
  21
  22 The interrupt is described in DT with IRQ_TYPE_LEVEL_HIGH
  23
  24 But the current compatible string uses the controller in edge triggered mode
  25 (as that config matches our register layout).
  26
  27 Add a new compatible structure for level driven interrupt with our register layout.
  28
  29 We had already been using this compatible string in device tree, so no change needed
  30 there.
  31
  32 Signed-off-by: Dom Cobley <popcornmix@gmail.com>
  33 ---
  34  drivers/irqchip/irq-brcmstb-l2.c | 17 +++++++++++++++++
  35  1 file changed, 17 insertions(+)
  36
  37 --- a/drivers/irqchip/irq-brcmstb-l2.c
  38 +++ b/drivers/irqchip/irq-brcmstb-l2.c
  39 @@ -51,6 +51,16 @@ static const struct brcmstb_intc_init_pa
  40         .cpu_mask_clear         = 0x0C
  41  };
  42
  43 +/* Register offsets in the 2711 L2 level interrupt controller */
  44 +static const struct brcmstb_intc_init_params l2_2711_lvl_intc_init = {
  45 +       .handler                = handle_level_irq,
  46 +       .cpu_status             = 0x00,
  47 +       .cpu_clear              = 0x08,
  48 +       .cpu_mask_status        = 0x0c,
  49 +       .cpu_mask_set           = 0x10,
  50 +       .cpu_mask_clear         = 0x14
  51 +};
  52 +
  53  /* L2 intc private data structure */
  54  struct brcmstb_l2_intc_data {
  55         struct irq_domain *domain;
  56 @@ -288,11 +298,18 @@ static int __init brcmstb_l2_lvl_intc_of
  57         return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
  58  }
  59
  60 +static int __init brcmstb_l2_2711_lvl_intc_of_init(struct device_node *np,
  61 +       struct device_node *parent)
  62 +{
  63 +       return brcmstb_l2_intc_of_init(np, parent, &l2_2711_lvl_intc_init);
  64 +}
  65 +
  66  IRQCHIP_PLATFORM_DRIVER_BEGIN(brcmstb_l2)
  67  IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_of_init)
  68  IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_of_init)
  69  IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_of_init)
  70  IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_of_init)
  71 +IRQCHIP_MATCH("brcm,bcm2711-l2-intc", brcmstb_l2_2711_lvl_intc_of_init)
  72  IRQCHIP_PLATFORM_DRIVER_END(brcmstb_l2)
  73  MODULE_DESCRIPTION("Broadcom STB generic L2 interrupt controller");
  74  MODULE_LICENSE("GPL v2");