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1 From 3d98604921d4b7216d3d0c8a76160dce083bd040 Mon Sep 17 00:00:00 2001
2 From: Devi Priya <quic_devipriy@quicinc.com>
3 Date: Fri, 25 Oct 2024 09:25:17 +0530
4 Subject: [PATCH 4/7] dt-bindings: clock: Add ipq9574 NSSCC clock and reset
5 definitions
6
7 Add NSSCC clock and reset definitions for ipq9574.
8
9 Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
10 Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
11 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12 ---
13 .../bindings/clock/qcom,ipq9574-nsscc.yaml | 73 +++++++++
14 .../dt-bindings/clock/qcom,ipq9574-nsscc.h | 152 ++++++++++++++++++
15 .../dt-bindings/reset/qcom,ipq9574-nsscc.h | 134 +++++++++++++++
16 3 files changed, 359 insertions(+)
17 create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
18 create mode 100644 include/dt-bindings/clock/qcom,ipq9574-nsscc.h
19 create mode 100644 include/dt-bindings/reset/qcom,ipq9574-nsscc.h
20
21 --- /dev/null
22 +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
23 @@ -0,0 +1,73 @@
24 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
25 +%YAML 1.2
26 +---
27 +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
28 +$schema: http://devicetree.org/meta-schemas/core.yaml#
29 +
30 +title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574
31 +
32 +maintainers:
33 + - Bjorn Andersson <andersson@kernel.org>
34 + - Anusha Rao <quic_anusha@quicinc.com>
35 +
36 +description: |
37 + Qualcomm networking sub system clock control module provides the clocks,
38 + resets and power domains on IPQ9574
39 +
40 + See also::
41 + include/dt-bindings/clock/qcom,ipq9574-nsscc.h
42 + include/dt-bindings/reset/qcom,ipq9574-nsscc.h
43 +
44 +properties:
45 + compatible:
46 + const: qcom,ipq9574-nsscc
47 +
48 + clocks:
49 + items:
50 + - description: Board XO source
51 + - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source
52 + - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source
53 + - description: GCC GPLL0 OUT AUX clock source
54 + - description: Uniphy0 NSS Rx clock source
55 + - description: Uniphy0 NSS Tx clock source
56 + - description: Uniphy1 NSS Rx clock source
57 + - description: Uniphy1 NSS Tx clock source
58 + - description: Uniphy2 NSS Rx clock source
59 + - description: Uniphy2 NSS Tx clock source
60 + - description: GCC NSSCC clock source
61 +
62 + '#interconnect-cells':
63 + const: 1
64 +
65 +required:
66 + - compatible
67 + - clocks
68 +
69 +allOf:
70 + - $ref: qcom,gcc.yaml#
71 +
72 +unevaluatedProperties: false
73 +
74 +examples:
75 + - |
76 + #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
77 + #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
78 + clock-controller@39b00000 {
79 + compatible = "qcom,ipq9574-nsscc";
80 + reg = <0x39b00000 0x80000>;
81 + clocks = <&xo_board_clk>,
82 + <&cmn_pll NSS_1200MHZ_CLK>,
83 + <&cmn_pll PPE_353MHZ_CLK>,
84 + <&gcc GPLL0_OUT_AUX>,
85 + <&uniphy 0>,
86 + <&uniphy 1>,
87 + <&uniphy 2>,
88 + <&uniphy 3>,
89 + <&uniphy 4>,
90 + <&uniphy 5>,
91 + <&gcc GCC_NSSCC_CLK>;
92 + #clock-cells = <1>;
93 + #reset-cells = <1>;
94 + #power-domain-cells = <1>;
95 + };
96 +...
97 --- /dev/null
98 +++ b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h
99 @@ -0,0 +1,152 @@
100 +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
101 +/*
102 + * Copyright (c) 2023, The Linux Foundation. All rights reserved.
103 + */
104 +
105 +#ifndef _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H
106 +#define _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H
107 +
108 +#define NSS_CC_CE_APB_CLK 0
109 +#define NSS_CC_CE_AXI_CLK 1
110 +#define NSS_CC_CE_CLK_SRC 2
111 +#define NSS_CC_CFG_CLK_SRC 3
112 +#define NSS_CC_CLC_AXI_CLK 4
113 +#define NSS_CC_CLC_CLK_SRC 5
114 +#define NSS_CC_CRYPTO_CLK 6
115 +#define NSS_CC_CRYPTO_CLK_SRC 7
116 +#define NSS_CC_CRYPTO_PPE_CLK 8
117 +#define NSS_CC_HAQ_AHB_CLK 9
118 +#define NSS_CC_HAQ_AXI_CLK 10
119 +#define NSS_CC_HAQ_CLK_SRC 11
120 +#define NSS_CC_IMEM_AHB_CLK 12
121 +#define NSS_CC_IMEM_CLK_SRC 13
122 +#define NSS_CC_IMEM_QSB_CLK 14
123 +#define NSS_CC_INT_CFG_CLK_SRC 15
124 +#define NSS_CC_NSS_CSR_CLK 16
125 +#define NSS_CC_NSSNOC_CE_APB_CLK 17
126 +#define NSS_CC_NSSNOC_CE_AXI_CLK 18
127 +#define NSS_CC_NSSNOC_CLC_AXI_CLK 19
128 +#define NSS_CC_NSSNOC_CRYPTO_CLK 20
129 +#define NSS_CC_NSSNOC_HAQ_AHB_CLK 21
130 +#define NSS_CC_NSSNOC_HAQ_AXI_CLK 22
131 +#define NSS_CC_NSSNOC_IMEM_AHB_CLK 23
132 +#define NSS_CC_NSSNOC_IMEM_QSB_CLK 24
133 +#define NSS_CC_NSSNOC_NSS_CSR_CLK 25
134 +#define NSS_CC_NSSNOC_PPE_CFG_CLK 26
135 +#define NSS_CC_NSSNOC_PPE_CLK 27
136 +#define NSS_CC_NSSNOC_UBI32_AHB0_CLK 28
137 +#define NSS_CC_NSSNOC_UBI32_AXI0_CLK 29
138 +#define NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK 30
139 +#define NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK 31
140 +#define NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK 32
141 +#define NSS_CC_PORT1_MAC_CLK 33
142 +#define NSS_CC_PORT1_RX_CLK 34
143 +#define NSS_CC_PORT1_RX_CLK_SRC 35
144 +#define NSS_CC_PORT1_RX_DIV_CLK_SRC 36
145 +#define NSS_CC_PORT1_TX_CLK 37
146 +#define NSS_CC_PORT1_TX_CLK_SRC 38
147 +#define NSS_CC_PORT1_TX_DIV_CLK_SRC 39
148 +#define NSS_CC_PORT2_MAC_CLK 40
149 +#define NSS_CC_PORT2_RX_CLK 41
150 +#define NSS_CC_PORT2_RX_CLK_SRC 42
151 +#define NSS_CC_PORT2_RX_DIV_CLK_SRC 43
152 +#define NSS_CC_PORT2_TX_CLK 44
153 +#define NSS_CC_PORT2_TX_CLK_SRC 45
154 +#define NSS_CC_PORT2_TX_DIV_CLK_SRC 46
155 +#define NSS_CC_PORT3_MAC_CLK 47
156 +#define NSS_CC_PORT3_RX_CLK 48
157 +#define NSS_CC_PORT3_RX_CLK_SRC 49
158 +#define NSS_CC_PORT3_RX_DIV_CLK_SRC 50
159 +#define NSS_CC_PORT3_TX_CLK 51
160 +#define NSS_CC_PORT3_TX_CLK_SRC 52
161 +#define NSS_CC_PORT3_TX_DIV_CLK_SRC 53
162 +#define NSS_CC_PORT4_MAC_CLK 54
163 +#define NSS_CC_PORT4_RX_CLK 55
164 +#define NSS_CC_PORT4_RX_CLK_SRC 56
165 +#define NSS_CC_PORT4_RX_DIV_CLK_SRC 57
166 +#define NSS_CC_PORT4_TX_CLK 58
167 +#define NSS_CC_PORT4_TX_CLK_SRC 59
168 +#define NSS_CC_PORT4_TX_DIV_CLK_SRC 60
169 +#define NSS_CC_PORT5_MAC_CLK 61
170 +#define NSS_CC_PORT5_RX_CLK 62
171 +#define NSS_CC_PORT5_RX_CLK_SRC 63
172 +#define NSS_CC_PORT5_RX_DIV_CLK_SRC 64
173 +#define NSS_CC_PORT5_TX_CLK 65
174 +#define NSS_CC_PORT5_TX_CLK_SRC 66
175 +#define NSS_CC_PORT5_TX_DIV_CLK_SRC 67
176 +#define NSS_CC_PORT6_MAC_CLK 68
177 +#define NSS_CC_PORT6_RX_CLK 69
178 +#define NSS_CC_PORT6_RX_CLK_SRC 70
179 +#define NSS_CC_PORT6_RX_DIV_CLK_SRC 71
180 +#define NSS_CC_PORT6_TX_CLK 72
181 +#define NSS_CC_PORT6_TX_CLK_SRC 73
182 +#define NSS_CC_PORT6_TX_DIV_CLK_SRC 74
183 +#define NSS_CC_PPE_CLK_SRC 75
184 +#define NSS_CC_PPE_EDMA_CFG_CLK 76
185 +#define NSS_CC_PPE_EDMA_CLK 77
186 +#define NSS_CC_PPE_SWITCH_BTQ_CLK 78
187 +#define NSS_CC_PPE_SWITCH_CFG_CLK 79
188 +#define NSS_CC_PPE_SWITCH_CLK 80
189 +#define NSS_CC_PPE_SWITCH_IPE_CLK 81
190 +#define NSS_CC_UBI0_CLK_SRC 82
191 +#define NSS_CC_UBI0_DIV_CLK_SRC 83
192 +#define NSS_CC_UBI1_CLK_SRC 84
193 +#define NSS_CC_UBI1_DIV_CLK_SRC 85
194 +#define NSS_CC_UBI2_CLK_SRC 86
195 +#define NSS_CC_UBI2_DIV_CLK_SRC 87
196 +#define NSS_CC_UBI32_AHB0_CLK 88
197 +#define NSS_CC_UBI32_AHB1_CLK 89
198 +#define NSS_CC_UBI32_AHB2_CLK 90
199 +#define NSS_CC_UBI32_AHB3_CLK 91
200 +#define NSS_CC_UBI32_AXI0_CLK 92
201 +#define NSS_CC_UBI32_AXI1_CLK 93
202 +#define NSS_CC_UBI32_AXI2_CLK 94
203 +#define NSS_CC_UBI32_AXI3_CLK 95
204 +#define NSS_CC_UBI32_CORE0_CLK 96
205 +#define NSS_CC_UBI32_CORE1_CLK 97
206 +#define NSS_CC_UBI32_CORE2_CLK 98
207 +#define NSS_CC_UBI32_CORE3_CLK 99
208 +#define NSS_CC_UBI32_INTR0_AHB_CLK 100
209 +#define NSS_CC_UBI32_INTR1_AHB_CLK 101
210 +#define NSS_CC_UBI32_INTR2_AHB_CLK 102
211 +#define NSS_CC_UBI32_INTR3_AHB_CLK 103
212 +#define NSS_CC_UBI32_NC_AXI0_CLK 104
213 +#define NSS_CC_UBI32_NC_AXI1_CLK 105
214 +#define NSS_CC_UBI32_NC_AXI2_CLK 106
215 +#define NSS_CC_UBI32_NC_AXI3_CLK 107
216 +#define NSS_CC_UBI32_UTCM0_CLK 108
217 +#define NSS_CC_UBI32_UTCM1_CLK 109
218 +#define NSS_CC_UBI32_UTCM2_CLK 110
219 +#define NSS_CC_UBI32_UTCM3_CLK 111
220 +#define NSS_CC_UBI3_CLK_SRC 112
221 +#define NSS_CC_UBI3_DIV_CLK_SRC 113
222 +#define NSS_CC_UBI_AXI_CLK_SRC 114
223 +#define NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC 115
224 +#define NSS_CC_UNIPHY_PORT1_RX_CLK 116
225 +#define NSS_CC_UNIPHY_PORT1_TX_CLK 117
226 +#define NSS_CC_UNIPHY_PORT2_RX_CLK 118
227 +#define NSS_CC_UNIPHY_PORT2_TX_CLK 119
228 +#define NSS_CC_UNIPHY_PORT3_RX_CLK 120
229 +#define NSS_CC_UNIPHY_PORT3_TX_CLK 121
230 +#define NSS_CC_UNIPHY_PORT4_RX_CLK 122
231 +#define NSS_CC_UNIPHY_PORT4_TX_CLK 123
232 +#define NSS_CC_UNIPHY_PORT5_RX_CLK 124
233 +#define NSS_CC_UNIPHY_PORT5_TX_CLK 125
234 +#define NSS_CC_UNIPHY_PORT6_RX_CLK 126
235 +#define NSS_CC_UNIPHY_PORT6_TX_CLK 127
236 +#define NSS_CC_XGMAC0_PTP_REF_CLK 128
237 +#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 129
238 +#define NSS_CC_XGMAC1_PTP_REF_CLK 130
239 +#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 131
240 +#define NSS_CC_XGMAC2_PTP_REF_CLK 132
241 +#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 133
242 +#define NSS_CC_XGMAC3_PTP_REF_CLK 134
243 +#define NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC 135
244 +#define NSS_CC_XGMAC4_PTP_REF_CLK 136
245 +#define NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC 137
246 +#define NSS_CC_XGMAC5_PTP_REF_CLK 138
247 +#define NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC 139
248 +#define UBI32_PLL 140
249 +#define UBI32_PLL_MAIN 141
250 +
251 +#endif
252 --- /dev/null
253 +++ b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h
254 @@ -0,0 +1,134 @@
255 +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
256 +/*
257 + * Copyright (c) 2023, The Linux Foundation. All rights reserved.
258 + */
259 +
260 +#ifndef _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H
261 +#define _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H
262 +
263 +#define EDMA_HW_RESET 0
264 +#define NSS_CC_CE_BCR 1
265 +#define NSS_CC_CLC_BCR 2
266 +#define NSS_CC_EIP197_BCR 3
267 +#define NSS_CC_HAQ_BCR 4
268 +#define NSS_CC_IMEM_BCR 5
269 +#define NSS_CC_MAC_BCR 6
270 +#define NSS_CC_PPE_BCR 7
271 +#define NSS_CC_UBI_BCR 8
272 +#define NSS_CC_UNIPHY_BCR 9
273 +#define UBI3_CLKRST_CLAMP_ENABLE 10
274 +#define UBI3_CORE_CLAMP_ENABLE 11
275 +#define UBI2_CLKRST_CLAMP_ENABLE 12
276 +#define UBI2_CORE_CLAMP_ENABLE 13
277 +#define UBI1_CLKRST_CLAMP_ENABLE 14
278 +#define UBI1_CORE_CLAMP_ENABLE 15
279 +#define UBI0_CLKRST_CLAMP_ENABLE 16
280 +#define UBI0_CORE_CLAMP_ENABLE 17
281 +#define NSSNOC_NSS_CSR_ARES 18
282 +#define NSS_CSR_ARES 19
283 +#define PPE_BTQ_ARES 20
284 +#define PPE_IPE_ARES 21
285 +#define PPE_ARES 22
286 +#define PPE_CFG_ARES 23
287 +#define PPE_EDMA_ARES 24
288 +#define PPE_EDMA_CFG_ARES 25
289 +#define CRY_PPE_ARES 26
290 +#define NSSNOC_PPE_ARES 27
291 +#define NSSNOC_PPE_CFG_ARES 28
292 +#define PORT1_MAC_ARES 29
293 +#define PORT2_MAC_ARES 30
294 +#define PORT3_MAC_ARES 31
295 +#define PORT4_MAC_ARES 32
296 +#define PORT5_MAC_ARES 33
297 +#define PORT6_MAC_ARES 34
298 +#define XGMAC0_PTP_REF_ARES 35
299 +#define XGMAC1_PTP_REF_ARES 36
300 +#define XGMAC2_PTP_REF_ARES 37
301 +#define XGMAC3_PTP_REF_ARES 38
302 +#define XGMAC4_PTP_REF_ARES 39
303 +#define XGMAC5_PTP_REF_ARES 40
304 +#define HAQ_AHB_ARES 41
305 +#define HAQ_AXI_ARES 42
306 +#define NSSNOC_HAQ_AHB_ARES 43
307 +#define NSSNOC_HAQ_AXI_ARES 44
308 +#define CE_APB_ARES 45
309 +#define CE_AXI_ARES 46
310 +#define NSSNOC_CE_APB_ARES 47
311 +#define NSSNOC_CE_AXI_ARES 48
312 +#define CRYPTO_ARES 49
313 +#define NSSNOC_CRYPTO_ARES 50
314 +#define NSSNOC_NC_AXI0_1_ARES 51
315 +#define UBI0_CORE_ARES 52
316 +#define UBI1_CORE_ARES 53
317 +#define UBI2_CORE_ARES 54
318 +#define UBI3_CORE_ARES 55
319 +#define NC_AXI0_ARES 56
320 +#define UTCM0_ARES 57
321 +#define NC_AXI1_ARES 58
322 +#define UTCM1_ARES 59
323 +#define NC_AXI2_ARES 60
324 +#define UTCM2_ARES 61
325 +#define NC_AXI3_ARES 62
326 +#define UTCM3_ARES 63
327 +#define NSSNOC_NC_AXI0_ARES 64
328 +#define AHB0_ARES 65
329 +#define INTR0_AHB_ARES 66
330 +#define AHB1_ARES 67
331 +#define INTR1_AHB_ARES 68
332 +#define AHB2_ARES 69
333 +#define INTR2_AHB_ARES 70
334 +#define AHB3_ARES 71
335 +#define INTR3_AHB_ARES 72
336 +#define NSSNOC_AHB0_ARES 73
337 +#define NSSNOC_INT0_AHB_ARES 74
338 +#define AXI0_ARES 75
339 +#define AXI1_ARES 76
340 +#define AXI2_ARES 77
341 +#define AXI3_ARES 78
342 +#define NSSNOC_AXI0_ARES 79
343 +#define IMEM_QSB_ARES 80
344 +#define NSSNOC_IMEM_QSB_ARES 81
345 +#define IMEM_AHB_ARES 82
346 +#define NSSNOC_IMEM_AHB_ARES 83
347 +#define UNIPHY_PORT1_RX_ARES 84
348 +#define UNIPHY_PORT1_TX_ARES 85
349 +#define UNIPHY_PORT2_RX_ARES 86
350 +#define UNIPHY_PORT2_TX_ARES 87
351 +#define UNIPHY_PORT3_RX_ARES 88
352 +#define UNIPHY_PORT3_TX_ARES 89
353 +#define UNIPHY_PORT4_RX_ARES 90
354 +#define UNIPHY_PORT4_TX_ARES 91
355 +#define UNIPHY_PORT5_RX_ARES 92
356 +#define UNIPHY_PORT5_TX_ARES 93
357 +#define UNIPHY_PORT6_RX_ARES 94
358 +#define UNIPHY_PORT6_TX_ARES 95
359 +#define PORT1_RX_ARES 96
360 +#define PORT1_TX_ARES 97
361 +#define PORT2_RX_ARES 98
362 +#define PORT2_TX_ARES 99
363 +#define PORT3_RX_ARES 100
364 +#define PORT3_TX_ARES 101
365 +#define PORT4_RX_ARES 102
366 +#define PORT4_TX_ARES 103
367 +#define PORT5_RX_ARES 104
368 +#define PORT5_TX_ARES 105
369 +#define PORT6_RX_ARES 106
370 +#define PORT6_TX_ARES 107
371 +#define PPE_FULL_RESET 108
372 +#define UNIPHY0_SOFT_RESET 109
373 +#define UNIPHY1_SOFT_RESET 110
374 +#define UNIPHY2_SOFT_RESET 111
375 +#define UNIPHY_PORT1_ARES 112
376 +#define UNIPHY_PORT2_ARES 113
377 +#define UNIPHY_PORT3_ARES 114
378 +#define UNIPHY_PORT4_ARES 115
379 +#define UNIPHY_PORT5_ARES 116
380 +#define UNIPHY_PORT6_ARES 117
381 +#define NSSPORT1_RESET 118
382 +#define NSSPORT2_RESET 119
383 +#define NSSPORT3_RESET 120
384 +#define NSSPORT4_RESET 121
385 +#define NSSPORT5_RESET 122
386 +#define NSSPORT6_RESET 123
387 +
388 +#endif
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