git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From fabcfd6d10999024a721ae1b965b57eb8a305ace Mon Sep 17 00:00:00 2001
   2 From: Heiner Kallweit <hkallweit1@gmail.com>
   3 Date: Sat, 15 Feb 2025 14:29:15 +0100
   4 Subject: [PATCH] net: phy: realtek: add defines for shadowed c45 standard
   5  registers
   6
   7 Realtek shadows standard c45 registers in VEND2 device register space.
   8 Add defines for these VEND2 registers, based on the names of the
   9 standard c45 registers.
  10
  11 Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
  12 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  13 Link: https://patch.msgid.link/c90bdf76-f8b8-4d06-9656-7a52d5658ee6@gmail.com
  14 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  15 ---
  16  drivers/net/phy/realtek/realtek_main.c | 33 +++++++++++++++++---------
  17  1 file changed, 22 insertions(+), 11 deletions(-)
  18
  19 --- a/drivers/net/phy/realtek/realtek_main.c
  20 +++ b/drivers/net/phy/realtek/realtek_main.c
  21 @@ -94,6 +94,16 @@
  22  #define RTL_VND2_PHYSR_MASTER                  BIT(11)
  23  #define RTL_VND2_PHYSR_SPEED_MASK              (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH)
  24
  25 +#define        RTL_MDIO_PCS_EEE_ABLE                   0xa5c4
  26 +#define        RTL_MDIO_AN_EEE_ADV                     0xa5d0
  27 +#define        RTL_MDIO_AN_EEE_LPABLE                  0xa5d2
  28 +#define        RTL_MDIO_AN_10GBT_CTRL                  0xa5d4
  29 +#define        RTL_MDIO_AN_10GBT_STAT                  0xa5d6
  30 +#define        RTL_MDIO_PMA_SPEED                      0xa616
  31 +#define        RTL_MDIO_AN_EEE_LPABLE2                 0xa6d0
  32 +#define        RTL_MDIO_AN_EEE_ADV2                    0xa6d4
  33 +#define        RTL_MDIO_PCS_EEE_ABLE2                  0xa6ec
  34 +
  35  #define RTL_GENERIC_PHYID                      0x001cc800
  36  #define RTL_8211FVD_PHYID                      0x001cc878
  37  #define RTL_8221B                              0x001cc840
  38 @@ -751,11 +761,11 @@ static int rtlgen_read_mmd(struct phy_de
  39         if (devnum == MDIO_MMD_VEND2)
  40                 ret = rtlgen_read_vend2(phydev, regnum);
  41         else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE)
  42 -               ret = rtlgen_read_vend2(phydev, 0xa5c4);
  43 +               ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE);
  44         else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV)
  45 -               ret = rtlgen_read_vend2(phydev, 0xa5d0);
  46 +               ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV);
  47         else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE)
  48 -               ret = rtlgen_read_vend2(phydev, 0xa5d2);
  49 +               ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE);
  50         else
  51                 ret = -EOPNOTSUPP;
  52
  53 @@ -770,7 +780,7 @@ static int rtlgen_write_mmd(struct phy_d
  54         if (devnum == MDIO_MMD_VEND2)
  55                 ret = rtlgen_write_vend2(phydev, regnum, val);
  56         else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV)
  57 -               ret = rtlgen_write_vend2(phydev, regnum, 0xa5d0);
  58 +               ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV);
  59         else
  60                 ret = -EOPNOTSUPP;
  61
  62 @@ -785,11 +795,11 @@ static int rtl822x_read_mmd(struct phy_d
  63                 return ret;
  64
  65         if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2)
  66 -               ret = rtlgen_read_vend2(phydev, 0xa6ec);
  67 +               ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2);
  68         else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2)
  69 -               ret = rtlgen_read_vend2(phydev, 0xa6d4);
  70 +               ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2);
  71         else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2)
  72 -               ret = rtlgen_read_vend2(phydev, 0xa6d0);
  73 +               ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2);
  74
  75         return ret;
  76  }
  77 @@ -803,7 +813,7 @@ static int rtl822x_write_mmd(struct phy_
  78                 return ret;
  79
  80         if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2)
  81 -               ret = rtlgen_write_vend2(phydev, 0xa6d4, val);
  82 +               ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val);
  83
  84         return ret;
  85  }
  86 @@ -899,7 +909,7 @@ static int rtl822x_get_features(struct p
  87  {
  88         int val;
  89
  90 -       val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xa616);
  91 +       val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED);
  92         if (val < 0)
  93                 return val;
  94
  95 @@ -920,7 +930,8 @@ static int rtl822x_config_aneg(struct ph
  96         if (phydev->autoneg == AUTONEG_ENABLE) {
  97                 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
  98
  99 -               ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 0xa5d4,
 100 +               ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2,
 101 +                                            RTL_MDIO_AN_10GBT_CTRL,
 102                                              MDIO_AN_10GBT_CTRL_ADV2_5G |
 103                                              MDIO_AN_10GBT_CTRL_ADV5G, adv);
 104                 if (ret < 0)
 105 @@ -966,7 +977,7 @@ static int rtl822x_read_status(struct ph
 106             !phydev->autoneg_complete)
 107                 return 0;
 108
 109 -       lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xa5d6);
 110 +       lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT);
 111         if (lpadv < 0)
 112                 return lpadv;
 113