RISC-V: Support const series vector for RVV auto-vectorization

RISC-V: Support const series vector for RVV auto-vectorization

This patch is the prerequiste patch for more RVV auto-vectorization
support.

Since when we enable a very simple binary operations, we will end
up with such following ICE:

during RTL pass: expand
add_run-1.c: In function 'main':
add_run-1.c:28:1: internal compiler error: Segmentation fault
0x1618ea3 crash_signal
	../../../riscv-gcc/gcc/toplev.cc:314
0xe76cd9 single_set(rtx_insn const*)
	../../../riscv-gcc/gcc/rtl.h:3602
0x1080f8a emit_move_insn(rtx_def*, rtx_def*)
	../../../riscv-gcc/gcc/expr.cc:4342
0x170c458 insert_value_copy_on_edge
	../../../riscv-gcc/gcc/tree-outof-ssa.cc:352
0x170d58e eliminate_phi
	../../../riscv-gcc/gcc/tree-outof-ssa.cc:785
0x170df17 expand_phi_nodes(ssaexpand*)
	../../../riscv-gcc/gcc/tree-outof-ssa.cc:1024
0xef27e2 execute
	../../../riscv-gcc/gcc/cfgexpand.cc:6818

This is because LoopVectorizer assume target is able to handle
series const vector when we enable binary operations.
Then it will be easily causing ICE like that.

gcc/ChangeLog:

	* config/riscv/autovec.md (@vec_series<mode>): New pattern
	* config/riscv/riscv-protos.h (expand_vec_series): New function.
	* config/riscv/riscv-v.cc (emit_binop): Ditto.
	(emit_index_op): Ditto.
	(expand_vec_series): Ditto.
	(expand_const_vector): Add series vector handling.
	* config/riscv/riscv.cc (riscv_const_insns): Enable series vector for testing.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/series-1.c: New test.
	* gcc.target/riscv/rvv/autovec/series_run-1.c: New test.