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drm/i915/psr: Split setting sff and cff bits away from intel_psr_force_update
authorJouni Högander <jouni.hogander@intel.com>
Thu, 13 Feb 2025 06:47:54 +0000 (08:47 +0200)
committerJouni Högander <jouni.hogander@intel.com>
Thu, 13 Feb 2025 14:41:22 +0000 (16:41 +0200)
commit005010f1f791a79d494ef83126425f587a4879cd
tree7dd2a38ee6b563e4aded3e8a1d48a7d5da0f2d53tree
parent8e8cadfd88b44b4ffb658ae6d6ab3bc61cfd7f35commit | diff
drm/i915/psr: Split setting sff and cff bits away from intel_psr_force_update

This is a clean-up and a preparation for adding own SFF and CFF registers
for LunarLake onwards.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250213064804.2077127-4-jouni.hogander@intel.com
drivers/gpu/drm/i915/display/intel_psr.c diff | blob | blame | history
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