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arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics
authorAndrea Corallo <andrea.corallo@arm.com>
Wed, 21 Oct 2020 09:16:01 +0000 (11:16 +0200)
committerAndrea Corallo <andrea.corallo@arm.com>
Fri, 11 Dec 2020 12:56:28 +0000 (13:56 +0100)
commit00b3e8408ab6173bedb5a0ad10c8cec17b8e99af
tree5539fd8291a07679ac39f5a0a6d0817239917a80tree
parentbc7d2977d108ed00c30c9f21d5701f28ffb50f29commit | diff
arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

gcc/ChangeLog

2020-10-21  Andrea Corallo  <andrea.corallo@arm.com>

* config/arm/arm_neon_builtins.def: Add to LOAD1LANE v4bf, v8bf.
* config/arm/arm_neon.h (vld1_lane_bf16, vld1q_lane_bf16): Add
intrinsics.

gcc/testsuite/ChangeLog

2020-10-21  Andrea Corallo  <andrea.corallo@arm.com>

* gcc.target/arm/simd/vld1_lane_bf16_1.c: New testcase.
* gcc.target/arm/simd/vld1_lane_bf16_indices_1.c: Likewise.
* gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c: Likewise.
gcc/config/arm/arm_neon.h diff | blob | blame | history
gcc/config/arm/arm_neon_builtins.def diff | blob | blame | history
gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c [new file with mode: 0644] blob
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