RISC-V: Fix autovec_length_operand predicate[PR110989]

RISC-V: Fix autovec_length_operand predicate[PR110989]

Currently, autovec_length_operand predicate incorrect configuration is
discovered in PR110989 since this following situation:

vect__6.24_107 = .MASK_LEN_LOAD (vectp.22_105, 32B, mask__49.21_99, POLY_INT_CST [2, 2], 0); ---> dummy length = VF.

The current autovec length operand failed to recognize the VF dummy length.

-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2:

Before this patch:

	srli	a4,s0,2
	addi	a4,a4,-3
	srli	s0,s0,3
	vsetvli	a5,zero,e64,m1,ta,ma
	vid.v	v1
	vmul.vx	v1,v1,a4
	addi	a4,s0,-2
	vadd.vx	v1,v1,a4
	addi	a4,s0,-1
	vslide1up.vx	v2,v1,a4
	vmv.v.x	v1,a4
	vand.vv	v1,v2,v1
	vl1re64.v	v3,0(t2)
	vrgather.vv	v2,v3,v1
	vmv.v.i	v1,0
	vmfeq.vv	v0,v2,v1
	vsetvli	zero,s0,e32,mf2,ta,ma    ---> s0 = POLY (2,2)
	vle32.v	v3,0(t3),v0.t
	vsetvli	a5,zero,e64,m1,ta,ma
	vmfne.vv	v0,v2,v1
	vsetvli	zero,zero,e32,mf2,ta,ma
	vfwcvt.f.x.v	v1,v3
	vsetvli	zero,zero,e64,m1,ta,ma
	vmerge.vvm	v1,v1,v2,v0
	vslidedown.vx	v1,v1,a4
	vfmv.f.s	fa5,v1
	j	.L6

After this patch:

	srli	a4,s0,2
	addi	a4,a4,-3
	srli	s0,s0,3
	vsetvli	a5,zero,e64,m1,ta,ma
	vid.v	v1
	vmul.vx	v1,v1,a4
	addi	a4,s0,-2
	vadd.vx	v1,v1,a4
	addi	s0,s0,-1
	vslide1up.vx	v2,v1,s0
	vmv.v.x	v1,s0
	vand.vv	v1,v2,v1
	vl1re64.v	v3,0(t2)
	vrgather.vv	v2,v3,v1
	vmv.v.i	v1,0
	vmfeq.vv	v0,v2,v1
	vle32.v	v3,0(t3),v0.t
	vmfne.vv	v0,v2,v1
	vsetvli	zero,zero,e32,mf2,ta,ma
	vfwcvt.f.x.v	v1,v3
	vsetvli	zero,zero,e64,m1,ta,ma
	vmerge.vvm	v1,v1,v2,v0
	vslidedown.vx	v1,v1,s0
	vfmv.f.s	fa5,v1
	j	.L6

2 vsetvli insns are reduced.

gcc/ChangeLog:

	PR target/110989
	* config/riscv/predicates.md: Fix predicate.

gcc/testsuite/ChangeLog:

	PR target/110989
	* gcc.target/riscv/rvv/autovec/pr110989.c: Add vsetvli assembly check.