]> git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V: Optimize comparison patterns for register allocation
authorJuzhe-Zhong <juzhe.zhong@rivai.ai>
Mon, 24 Apr 2023 03:53:41 +0000 (11:53 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Wed, 26 Apr 2023 03:58:17 +0000 (11:58 +0800)
commit06792c142c5ac8424db1ca36d11b0b9d42de3f21
tree5c23c16a1e5deac5b4f132a14ebad9a8d474d5f2
parent4f9eac2f262dfe938edf52045ef3fcdcf925af2d
RISC-V: Optimize comparison patterns for register allocation

Current RA constraint for RVV comparison instructions totall does not allow
registers between dest and source operand have any overlaps.

For example:
  vmseq.vv vd, vs2, vs1
If LMUL = 8, vs2 = v8, vs1 = v16:

In current GCC RA constraint, GCC does not allow vd to be any regno in v8 ~ v23.
However, it is too conservative and not true according to RVV ISA.

Since the dest EEW of comparison is always EEW = 1, so it always follows the overlap
rules of Dest EEW < Source EEW. So in this case, we should allow GCC RA have the chance
to allocate v8 or v16 for vd, so that we can have better vector registers usage in RA.

gcc/ChangeLog:

* config/riscv/vector.md (*pred_cmp<mode>_merge_tie_mask): New pattern.
(*pred_ltge<mode>_merge_tie_mask): Ditto.
(*pred_cmp<mode>_scalar_merge_tie_mask): Ditto.
(*pred_eqne<mode>_scalar_merge_tie_mask): Ditto.
(*pred_cmp<mode>_extended_scalar_merge_tie_mask): Ditto.
(*pred_eqne<mode>_extended_scalar_merge_tie_mask): Ditto.
(*pred_cmp<mode>_narrow_merge_tie_mask): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/binop_vv_constraint-4.c: Adapt testcase.
* gcc.target/riscv/rvv/base/narrow_constraint-17.c: New test.
* gcc.target/riscv/rvv/base/narrow_constraint-18.c: New test.
* gcc.target/riscv/rvv/base/narrow_constraint-19.c: New test.
* gcc.target/riscv/rvv/base/narrow_constraint-20.c: New test.
* gcc.target/riscv/rvv/base/narrow_constraint-21.c: New test.
* gcc.target/riscv/rvv/base/narrow_constraint-22.c: New test.
* gcc.target/riscv/rvv/base/narrow_constraint-23.c: New test.
* gcc.target/riscv/rvv/base/narrow_constraint-24.c: New test.
* gcc.target/riscv/rvv/base/narrow_constraint-25.c: New test.
* gcc.target/riscv/rvv/base/narrow_constraint-26.c: New test.
* gcc.target/riscv/rvv/base/narrow_constraint-27.c: New test.
* gcc.target/riscv/rvv/base/narrow_constraint-28.c: New test.
* gcc.target/riscv/rvv/base/narrow_constraint-29.c: New test.
* gcc.target/riscv/rvv/base/narrow_constraint-30.c: New test.
* gcc.target/riscv/rvv/base/narrow_constraint-31.c: New test.
17 files changed:
gcc/config/riscv/vector.md
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-4.c
gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-17.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-18.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-19.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-20.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-21.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-22.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-23.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-24.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-25.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-26.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-27.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-28.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-29.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-30.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-31.c [new file with mode: 0644]