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(parent: 30d82dd) | patch
perf/x86/intel: Update event constraints for DMR
authorDapeng Mi <dapeng1.mi@linux.intel.com>
Fri, 15 May 2026 06:11:35 +0000 (14:11 +0800)
committerPeter Zijlstra <peterz@infradead.org>
Tue, 19 May 2026 11:49:03 +0000 (13:49 +0200)
commit070bd45e1dba684bfa4e7fdaa8ef8efa99b4572e
tree7291c2783e371af78e5d657fb04553596079f9fatree | snapshot
parent30d82ddee085b4b0f9a1b5bded53acaca68d9a52commit | diff
perf/x86/intel: Update event constraints for DMR

Add missed event constraint for 0x0200 event and add comments to show
the event names in pnc_hw_cache_extra_regs[].

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260515061143.338553-4-dapeng1.mi@linux.intel.com
arch/x86/events/intel/core.c diff | blob | blame | history
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