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clk: renesas: r9a09g056: Add clock and reset entries for ISP
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thu, 23 Oct 2025 21:07:24 +0000 (22:07 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 27 Oct 2025 11:15:00 +0000 (12:15 +0100)
commit07525a693a5ff6592668a0fd647153e4b4933cae
treee299a289e46c4812db0a3542b946def71acc855atree | snapshot
parent861df8792c69d903fbb705a0d314bfdd5546d72bcommit | diff
clk: renesas: r9a09g056: Add clock and reset entries for ISP

Add entries detailing the clocks and resets for the ISP in the
RZ/V2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251023210724.666476-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a09g056-cpg.c diff | blob | blame | history
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