[committed] Fix missing mode on a few unspec/unspec_volatile operands
This is fix for a minor problem Jivan and I found while testing the ext-dce work originally from Joern.
The ext-dce pass will transform zero/sign extensions into subreg accesses when
the upper bits are actually unused. So it's more likely with the ext-dce work
to get a sequence like this prior to combine:
When we try to combine insn 10->11 we'll ultimately call simplify_subreg with
something like
(subreg:DI (unspec_volatile [...]) 0)
Note the lack of a mode on the unspec_volatile. That in turn will cause
simplify_subreg to trigger an assertion.
The modeless unspec is generated by the RISC-V backend and the more I've
pondered this issue over the last few days the more I'm convinced it's a
backend bug. Basically if the LHS of the set has a mode, then the RHS of the
set should have a mode as well.
I've audited the various backends and only found a few problems which are fixed
by this patch. I've tested the relevant ports in my tester. c6x, sh, mips and
s390[x].
There are other patterns that are potentially problematical in various ports.
They have a REG destination and an UNSPEC source, but the REG has no mode in
the pattern. Since it wasn't clear what mode to give the UNSPEC, I left those
alone.