rs6000, Add new overloaded vector shift builtin int128 variants

rs6000, Add new overloaded vector shift builtin int128 variants

Add the signed __int128 and unsigned __int128 argument types for the
overloaded built-ins vec_sld, vec_sldb, vec_sldw, vec_sll, vec_slo,
vec_srdb, vec_srl, vec_sro.  For each of the new argument types add a
testcase and update the documentation for the built-in.

gcc/ChangeLog:
	* config/rs6000/altivec.md (vs<SLDB_lr>db_<mode>): Change
	define_insn iterator to VEC_IC.
	* config/rs6000/rs6000-builtins.def (__builtin_altivec_vsldoi_v1ti,
	__builtin_vsx_xxsldwi_v1ti, __builtin_altivec_vsldb_v1ti,
	__builtin_altivec_vsrdb_v1ti): New builtin definitions.
	* config/rs6000/rs6000-overload.def (vec_sld, vec_sldb, vec_sldw,
	vec_sll, vec_slo, vec_srdb, vec_srl, vec_sro): New overloaded
	definitions.
	* doc/extend.texi (vec_sld, vec_sldb, vec_sldw, vec_sll, vec_slo,
	vec_srdb, vec_srl, vec_sro): Add documentation for new overloaded
	built-ins.

gcc/testsuite/ChangeLog:
	* gcc.target/powerpc/vec-shift-double-runnable-int128.c: New test
	file.