Fix various RISC-V testsuite regressions after volatile patch

Fix various RISC-V testsuite regressions after volatile patch

The RISC-V port showed a handful of regressions after integrating the final
patch from HJ for volatile accesses.

The core issue is the RISC-V port has two patterns which are basically the same
RTL form with the exception of a clobber of a scratch operand.

Those patterns do differ materially in their condition in that one is more
strict than the other.  The pattern with the stricter condition also happens to
be the one without the clobber.  So it's clearly stricter across both of those
axis.

The stricter pattern naturally generates more efficient (loopless) code for the
relevant atomic operations.  We have a handful of tests in the RISC-V port
which verify that we use the right sequences.

With HJ's patch the insn gets re-matched during combine which adds the clobber
and ultimately matches the more general pattern (which is currently first in
the MD file).  So we end up with the less efficient sequence and the relevant
tests naturally fail.

This patch just puts the two patterns in the right order with the stricter
pattern coming first.  I also walked through the rest of the sync.md patterns
and none obviously had the same problem.

This has been bootstrapped and regression tested on risc-v with both the
Pioneer and BPI F3 systems.

I'll let pre-commit CI chew on it overnight before the planned commit tomorrow.

jeff

gcc/
	* config/riscv/sync.md (atomic compare and set): Reorder patterns
	so the stricter pattern comes first.